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W641GG2JB 1 - gbit gddr 3 graphics sdram publication release date: apr, 22 , 20 11 - 1 - revision a01 - 002 table of contents 1. general description ................................ ................................ ................................ .......... 6 2. features ................................ ................................ ................................ ................................ .. 7 3. pin configuration ................................ ................................ ................................ ................ 8 3.1 ballout 1 - cs non - m e rged mode (top view, mf=0) ................................ ................................ ............. 8 3.2 ballout 2 - cs non - m e rged mode (top view, mf=0) ................................ ................................ ............. 9 3.3 b a l l o u t m e rg e d mode (top view, mf=0) ................................ ................................ ........................... 10 4. pin description ................................ ................................ ................................ .................... 11 4.1 signal des cription ................................ ................................ ................................ .............................. 11 4.2 addressing ................................ ................................ ................................ ................................ ........ 12 5. state diagram ................................ ................................ ................................ ..................... 13 5.1 s tate diagram for one activated bank ................................ ................................ ............................... 13 5.1.1 state diagram for one bank ................................ ................................ ................................ ............................. 13 5.1.2 f unction truth table for more than one activated bank ................................ ................................ .................. 14 5.1.2.1 fun c tio n tr u t h t a bl e ................................ ................................ ................................ ................................ ................... 14 5.1.3 f unction truth table for cke ................................ ................................ ................................ .......................... 15 5.2 f u nctio n al block diagram in 1 - cs mo d e ................................ ................................ ........................... 16 5.3 functional block diagram in 2 - cs mode ................................ ................................ ........................... 17 6. f unctional description ................................ ................................ ................................ ... 18 6.1 system configurations ................................ ................................ ................................ ....................... 18 6.1.1 system configurations in 1 - cs mode and 2 - cs mode ................................ ................................ ................... 18 6.1.2 initialization in 1 C cs mode ................................ ................................ ................................ ............................. 19 6.1.3 initialization in 2 C cs mode ................................ ................................ ................................ ............................. 20 6.1.3.1 power up sequence ................................ ................................ ................................ ................................ ................... 21 .2 m irror function ................................ ................................ ................................ ................................ .... 22 6.2.1 ball assignment with mirror function ................................ ................................ ................................ .............. 22 6.3 commands ................................ ................................ ................................ ................................ ........ 23 6.3.1 c o m ma n d o v e rv i ew f or 1 - cs m od e ................................ ................................ ................................ ................ 23 6.3.2 c o m ma n d o v e rv i ew f or 2 - cs m od e ................................ ................................ ................................ ................ 24 6.3.3 description of command ................................ ................................ ................................ ................................ . 25 6.3.4 minimum delay f r om rd/a and wr/a to any other command (to another bank) with concurre n t ap ............. 28 6.4 boundary scan ................................ ................................ ................................ ................................ .. 28 6.4.1 general description ................................ ................................ ................................ ................................ ......... 28 6.4.2 disabling the scan feature ................................ ................................ ................................ ............................... 28 6.4.2.1 internal block diagram (reference only) ................................ ................................ ................................ .................... 29 6.4.2.2 boundary scan exit o r der ................................ ................................ ................................ ................................ ........... 29 6.4.2.3 scan pin description ................................ ................................ ................................ ................................ ................... 30 6.4.2.4 scan dc electrical characteristics and ope r ating condition ................................ ................................ ....................... 30 6.4.2.5 scan capture timing ................................ ................................ ................................ ................................ ................... 31 www.datasheet.co.kr datasheet pdf - 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W641GG2JB 1 - gbit gddr 3 graphics sdram publication release date: apr, 22 , 20 11 - 2 - revision a01 - 002 6.4.2.6 scan shift timing ................................ ................................ ................................ ................................ ........................ 31 6.4.2. 7 scan ac electrical characteristic ................................ ................................ ................................ ................................ 32 6.4.3 s can initialization ................................ ................................ ................................ ................................ ............. 32 6.4.3.1 s can initialization for stand - alone mode ................................ ................................ ................................ ..................... 32 6.4.3.2 scan initialization for stand - alone mode ................................ ................................ ................................ .................... 33 6.4.4 s can initialization in regular sgram operation ................................ ................................ ............................... 33 6.4.4.1 scan initialization sequence within regular sgram mode ................................ ................................ ......................... 34 6.4.5 s can exit sequence ................................ ................................ ................................ ................................ ........ 35 6.4.5.1 boundary scan exit sequence ................................ ................................ ................................ ................................ ... 35 6.4.5.2 scan ac electrical parameter ................................ ................................ ................................ ................................ ..... 35 6.5 p rogrammable impedance output drivers and active terminations ................................ ...................... 36 6.5.1 gddr3 io driver and termination ................................ ................................ ................................ .................. 36 6.5.1.1 output deiver simplified schematic ................................ ................................ ................................ ............................. 37 6.5.1.2 ra n ge of external resistance zq ................................ ................................ ................................ ................................ . 37 6.5.1.3 termination types and activation ................................ ................................ ................................ ............................... 37 6.5.2 s elf calibration for driver and termination ................................ ................................ ................................ ...... 38 6.5.2.1 termination update keep out time after autorefresh command ................................ ................................ ................. 38 6.5.2.2 n u mbe r o f l eg s u se d f o r te r m in a t or a n d dr i ve r s e l f c a l i br a t i o n ................................ ................................ ................ 39 6.5.2.3 self calibration of pmos and nmos legs ................................ ................................ ................................ ................. 39 6.5.3 dynamic switching of dq terminations ................................ ................................ ................................ ............ 40 6.5.3.1 odt disable timing during a read command ................................ ................................ ................................ .......... 40 6.5.4 output impedance and ter m ination dc electrical characteristics ................................ ................................ .. 41 6.5.4.1 dc electrical characteristic ................................ ................................ ................................ ................................ ......... 41 6.6 m ode register set command (mrs) ................................ ................................ ................................ . 42 6.6.1 mode register set command ................................ ................................ ................................ ......................... 42 6.6.2 mode registers ................................ ................................ ................................ ................................ ................ 42 6.6.2.1 mode register (mrs) ................................ ................................ ................................ ................................ ................. 42 6.6. 2.2 mode register (mrs) ................................ ................................ ................................ ................................ ................. 43 6.6.2.3 mode register set timing ................................ ................................ ................................ ................................ ........... 43 6.6.3 burst length and burst type ................................ ................................ ................................ ........................... 44 6.6.3.1 burst length ................................ ................................ ................................ ................................ ................................ 44 6.6.3.2 b urs t type ................................ ................................ ................................ ................................ ................................ .... 44 6.6.4 cas latency ................................ ................................ ................................ ................................ .................... 44 6.6.5 w rite latency ................................ ................................ ................................ ................................ ................... 44 6.6.6 dll reset ................................ ................................ ................................ ................................ ........................ 45 6.6.7 t est mode ................................ ................................ ................................ ................................ ........................ 45 6.7 e xtended mode register set command (emrs1) ................................ ................................ ............. 45 6.7.1 extended mode register set command ................................ ................................ ................................ ......... 46 6.7.2 extended mode register 1 (emrs1) ................................ ................................ ................................ .............. 46 6.7.2.1 extended mode register 1 (emrs1) ................................ ................................ ................................ .......................... 47 6.7.2.2 extended mode register set timing ................................ ................................ ................................ .......................... 48 6.7.3 chip select mode ................................ ................................ ................................ ................................ ............ 48 6.7.4 dll ................................ ................................ ................................ ................................ ................................ .. 48 6.7.5 write recovery ................................ ................................ ................................ ................................ ................ 48 www.datasheet.co.kr datasheet pdf - http://www..net/
W641GG2JB 1 - gbit gddr 3 graphics sdram publication release date: apr, 22 , 20 11 - 3 - revision a01 - 002 6.7.6 t ermination rtt ................................ ................................ ................................ ................................ ................ 48 6.7.7 impedance autocalibration of output buffer and active terminator ................................ ............................... 49 6.7.7.1 impedance options ................................ ................................ ................................ ................................ ..................... 49 6.7.7.2 timing of vendor code and revision id generation on dq[7:0] ................................ ................................ ................ 49 6.7.8 output driver impedance ................................ ................................ ................................ ................................ . 50 6.7.9 data termination ................................ ................................ ................................ ................................ ............. 50 6.7.10 a dd ress command termination ................................ ................................ ................................ ...................... 50 6.8 e xtended mode register 2 set command (emrs2) ................................ ................................ .......... 50 6.8.1 extended mode register 2 set command ................................ ................................ ................................ ...... 51 6.8.2 extended mode register 2 (emrs2) ................................ ................................ ................................ .............. 51 6.8.2.1 extended mode register 2 (emrs2) ................................ ................................ ................................ .......................... 52 6.8.2.2 impedance offsets ................................ ................................ ................................ ................................ ...................... 5 2 6.8.2. 3 merged mode ................................ ................................ ................................ ................................ .............................. 52 6.8.3 ocd pull down offset ................................ ................................ ................................ ................................ ..... 52 6.8.4 odt pull up offset ................................ ................................ ................................ ................................ .......... 52 6.9 extended mode register 3 (emrs3) ................................ ................................ ................................ . 53 6.10 v endor code and revision id ................................ ................................ ................................ .......... 53 6.10.1 vendor id code ................................ ................................ ................................ ................................ ............. 53 6.11 b ank / row activation (act) ................................ ................................ ................................ ............ 54 6.11.1 activating a specific row ................................ ................................ ................................ ................................ 54 6.11.2 bank activation timing ................................ ................................ ................................ ................................ .. 55 6.11.3 bank activation timing on different rank in 2 - cs mode ................................ ................................ ................ 55 6.11.4 four window active tfaw ................................ ................................ ................................ ............................. 55 6.11.5 clock, cke and command / address timings ................................ ................................ .............................. 56 6.12 bank activations with refresh ................................ ................................ ................................ ..... 56 6.12.1 bank activations with refresh command ................................ ................................ ................................ . 56 6.13 w rites (wr) ................................ ................................ ................................ ................................ ..... 57 6.13.1 w rite - basic information ................................ ................................ ................................ ............................... 57 6.13.1.1 write command ................................ ................................ ................................ ................................ ........................ 58 6.13.1.2 mapping of wdqs and dm signals ................................ ................................ ................................ .......................... 58 6.13.1.3 basic write burst / dm timing ................................ ................................ ................................ ................................ .. 59 6.14 w rite - basic sequence ................................ ................................ ................................ ................... 60 6.15 w rite - consecutive bursts ................................ ................................ ................................ ............... 61 6.15.1gapless bursts ................................ ................................ ................................ ................................ ................ 61 6.15.1.1 gapless write bursts ................................ ................................ ................................ ................................ ................ 61 6.15.2 b ursts with gaps ................................ ................................ ................................ ................................ ............ 62 6.15.2.1 consecutive write bursts with gaps ................................ ................................ ................................ ......................... 62 6.15.3 w rite with autoprecharge ................................ ................................ ................................ .............................. 63 6.15.4 w rite followed by read ................................ ................................ ................................ ................................ .. 64 6.15.5 w rite followed by read on different ranks in 2 - cs mode ................................ ................................ ............... 65 6.15.6 w rite followed by dterdis ................................ ................................ ................................ ........................... 66 6.15.7 w rite with autoprecharge followed by read / read with autoprecharge on another bank ........................... 67 6.15.8 w rite followed by precharge on same bank ................................ ................................ ................................ ... 68 www.datasheet.co.kr datasheet pdf - http://www..net/
W641GG2JB 1 - gbit gddr 3 graphics sdram publication release date: apr, 22 , 20 11 - 4 - revision a01 - 002 6.16 reads (rd) ................................ ................................ ................................ ................................ ...... 69 6.16.1 read - basic information ................................ ................................ ................................ ............................... 69 6.16.1.1 read command ................................ ................................ ................................ ................................ ........................ 70 6.16.1.2 basic read burst timing ................................ ................................ ................................ ................................ ........... 71 6.16.2 read - basic sequence ................................ ................................ ................................ ................................ . 72 6.16.2.1 read burst ................................ ................................ ................................ ................................ ................................ 72 6.16.3 conse cutive read bursts ................................ ................................ ................................ .............................. 73 6.16.3.1 gapless bursts ................................ ................................ ................................ ................................ .......................... 73 6.16.4 b ursts with gaps ................................ ................................ ................................ ................................ ............ 74 6.16.4.1 consecutive read bursts with gaps ................................ ................................ ................................ ......................... 74 6.16.5 read followed by dterdis ................................ ................................ ................................ ........................... 75 6.16.6 read with autoprecharge ................................ ................................ ................................ .............................. 76 6. 16.7 read followed by write ................................ ................................ ................................ ................................ .. 77 6.16.8 read followed by p r echarge on the same bank ................................ ................................ ............................ 78 6.17 data termination disable (dterdis) ................................ ................................ .............................. 79 6.17.1 data terminal disable command ................................ ................................ ................................ ................. 79 617.1.1 dterdis timing ................................ ................................ ................................ ................................ ....................... 80 6.17.2 dte rdis followed by dterdis ................................ ................................ ................................ ................... 81 6.17.3 dterdis followed by read ................................ ................................ ................................ ......................... 82 6.17.4 dterdis followed by write ................................ ................................ ................................ ........................... 83 6.18 precharge (pre/preall) ................................ ................................ ................................ ............... 84 6.18 .1 precharge command ................................ ................................ ................................ ................................ .... 84 6.18.2 ba2, ba1 and ba0 precha r ge bank selection within one rank ................................ ................................ ...... 85 6.18.3 precharge timing ................................ ................................ ................................ ................................ .......... 85 6.19 auto refresh command (aref) ................................ ................................ ................................ ...... 86 6.19.1 auto refresh command ................................ ................................ ................................ ................................ 86 6.19 .2 auto refresh cycle ................................ ................................ ................................ ................................ ........ 87 6.20 self - refresh ................................ ................................ ................................ ................................ .... 87 6.20.1 s elf - refresh entry (srefen) ................................ ................................ ................................ ........................ 87 6.20.1.1 self - refresh entry command ................................ ................................ ................................ ................................ ... 88 6.20.1.2 self refresh entry ................................ ................................ ................................ ................................ ..................... 89 6.21 self - refresh exit (srefex) ................................ ................................ ................................ ............. 89 6.21.1 self refresh exit command ................................ ................................ ................................ .......................... 90 6.21.2 self refresh exit ................................ ................................ ................................ ................................ ............ 90 6.22 power - down ................................ ................................ ................................ ................................ .... 91 6.22.1 power down command ................................ ................................ ................................ ................................ . 91 6.22.2 power - down mode ................................ ................................ ................................ ................................ ........ 92 7 electrical characteristics ................................ ................................ ........................... 93 7.1 a bsolute maximum ratings and operation conditions ................................ ................................ ....... 93 7.1.1 absolute maxi m um rating ................................ ................................ ................................ ............................... 93 7.2 dc operation conditions ................................ ................................ ................................ ................... 93 7.2.1 recommended power & dc operation conditions ................................ ................................ ......................... 93 www.datasheet.co.kr datasheet pdf - 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W641GG2JB 1 - gbit gddr 3 graphics sdram publication release date: apr, 22 , 20 11 - 5 - revision a01 - 002 7.2.1.1 power & dc operation cond i tions (0 c t c 1 05 c) ................................ ................................ ............................ 93 7.3 dc & ac logic input levels ................................ ................................ ................................ ............... 94 7.3.1 dc & ac logic input levels (0 c t c 1 05 c) ................................ ................................ .......................... 94 7.4 differential clock dc and ac levels ................................ ................................ ................................ .. 95 7.4.1 differential clock dc and ac input conditions (0 c t c 105c) ................................ ............................... 95 7.5 output test conditions ................................ ................................ ................................ ...................... 95 7.6 p in capacitances ................................ ................................ ................................ ............................... 96 7.6.1 pin c apac i tances (vd d q = 1.8 v, ta = 25c, f = 1 m hz) ................................ ................................ .............. 96 7.7 driver current characteristics ................................ ................................ ................................ ............. 96 7.7.1 driver iv characteristics at 40 ohms ................................ ................................ ................................ ................ 96 7.7.1.1 40 ohm driver pull - down and pull - up characteristics ................................ ................................ ................................ 96 7.7.1.2 prog r ammed driver iv characteristics at 40 ohm ................................ ................................ ................................ ....... 97 7.8 termination current characteristics ................................ ................................ ................................ .... 97 7.8.1 t ermination iv characteristic at 60 ohms ................................ ................................ ................................ ....... 97 7.8.1.1 60 ohm active termination characteristic ................................ ................................ ................................ .................. 98 7.8.1.2 prog r ammed terminator characteristics at 60 ohm ................................ ................................ ................................ .... 98 7.8.2 t ermination iv characteristic at 120 ohms ................................ ................................ ................................ ..... 99 7.8.2.1 120 ohm active termination characteristic ................................ ................................ ................................ ................ 99 7.8.2.2 programmed te r minator characteristics of 120 ohm ................................ ................................ ................................ 100 7.8.3 t ermination iv characteristic at 240 ohms ................................ ................................ ................................ ... 100 7.8.3.1 240 ohm active termination characteristic ................................ ................................ ................................ .............. 100 7.8.3.2 pr og ra m med te rmi n a to r c h ar a c te r i s t i c s at 2 40 oh m ................................ ................................ ............................... 101 7.9 operating current ratings ................................ ................................ ................................ ............... 102 7. 10 ac timings ................................ ................................ ................................ ................................ .... 103 8. package spec ification ................................ ................................ ................................ ... 106 9. ordering informat ion ................................ ................................ ................................ .... 107 10. revi sion history ................................ ................................ ................................ ............. 108 www.datasheet.co.kr datasheet pdf - http://www..net/
W641GG2JB 1 - gbit gddr 3 graphics sdram publication release date: apr, 22 , 20 11 - 6 - revision a01 - 002 1. general description t h e W641GG2JB 1 - g b it gddr 3 graphics sdram is a hi g h s p eed dyn a m i c ran d om - access memory desi g ned for a p pl i c a t i ons r e qu i r i ng hi g h ba n dwi d th. it contai n s 1,0 7 3,741 , 8 2 4 bits. t h e device can b e c o nfig u r e d to o p erate in two different m o des: ? i n 2 - cs mo d e t h e chip is or g aniz e d as two 512 m b it m e m o ries of 8 banks e a ch, with 4 096 r o w l o c a t i ons and 5 1 2 column l o cat i ons per ba n k. ? i n 1 - cs m o de the chip is org a nized as o n e 1 gb i t memor y , with 8 192 row l o cations a nd 5 12 c o lumn l o catio n s per bank. t h e gddr3 graphics sdram us e s a do u ble data rate a rchitecture to ach i eve high sp e ed op e r a t i on. the d o uble d a ta rate arch i t ecture is esse n t i a lly a 4n prefetch arch i t e c ture with an i n terface desi g ned to tr a n sf e r t w o d a ta words p e r clock cycle at the i/o p i ns. a single read or write ac c e ss for the gddr3 graphics sdram effective l y consists of a 4n data tran s fer every two clock cycles a t the inter n al d r am c o re a n d four c o rr e spon d ing n - bit w i de, o n e - ha l f - cl o c k - cycle data tr a n sfers a t t h e i/o p i ns. un i d irectio n al d a ta strob e s are transm i tted ext e rnal l y, a lo n g with data, for use in data c a pture a t the rece i v e r. r dqs is a strobe tr a n smitted by t h e gddr3 graphics sdram duri n g r e a d s. w dqs is the d a ta str o be sent by t h e memory control l er d u ring w ri t es. rdqs is edg e - ali g ned with data f o r reads and w d qs i s ce n t er - a lig n ed with d a ta for wr it es. t h e gddr3 graphics sdram o p erates from a d i ffere n t i al clock (clk a n d c lk # ; the crossi n g of c l k goi n g high and clk # go i ng l o w w ill be r e ferr e d to as the p o s i t i ve clk edg e ). comma n d s ( a ddress and c o ntr o l sign a ls) a re r e gistered a t the pos i t ive c l k edg e . inp u t d a ta is re g ist e r e d at b o th ed g es of w dqs, and o u t p ut d a ta is r e f e renced to b o th e d ges of r dqs, as w e ll as to b o th e dg e s of clk. re a d a nd write accesses to the gddr3 graphics sdram a re b u rst o r i e nted. t h e b u rst len g th can b e p rogrammed to 4 o r 8 and the two l east si g n ifica n t bits o f t h e b u rst ad d ress are Ddo n t car e a n d i n t e rnal l y set to low. accesses start a t a sel e cted l o cation a n d c o ntinue for a t o t a l o f four or eig h t loc a t i ons. accesses be g in with t h e registration of an active c o mm a nd, w h ich is t h en foll o wed by a read o r w ri t e c o mm a nd. the a d dress bits re g istered coi n c i de n t with t h e a c tive command are us e d to select the b ank a nd t h e r o w to be accesse d . t h e a ddress bits re g istered coi n cide n t w i th t h e read o r w rite command are u sed to se l e ct the ba n k and the st a rti n g col u mn loc a t i on for the burst access. www.datasheet.co.kr datasheet pdf - http://www..net/
W641GG2JB 1 - gbit gddr 3 graphics sdram publication release date: apr, 22 , 20 11 - 7 - revision a01 - 002 2. features ? de n sity: 1g b it ? pow e r su p p ly (v d d, vddq): 1.8v 0.1v ? o r g aniz a t i on: 1 chip select x 8 ba n ks x 4m w o rds x 32 b its (1 - cs mode) and 2 chip select x 8 ba n ks x 2m w o rds x 32 b i ts (2 - cs m o de) ? eig h t inter n al ba n ks p e r chip select for c o ncurre n t op e ration ? 4n pr e f etch arch i t ecture: 128 b it p e r a r r a y r e ad or write access ? double - data rate a r chitectu r e : two data t r ansfers per clock cycle ? sin g le en d ed interface for d a ta, a ddress and comma n d ? differenti a l c l ock i nputs clk, clk # ? comman d s e n tered on e a ch positive clk e d ge ? sin g le en d ed re a d stro b e ( r dqs) per byte, e d ge - a l ig n ed with read d a ta ? single en d ed write str o be (wdqs) p e r b yt e , center - a l ign e d with write data ? w rite da t a mask (d m ) function ? dll a lig n s dq and rdqs tra n s i t i ons with clk clock edg e s for rea d s ? burst l e ngth (bl): 4 or 8 ? seq u ential b u rst ty p e on l y ? programma b le cas l a tency: 7 to 14 ? programma b le write late n cy: 3 to 7 ? auto prech a r g e option for each b u rst access ? pseu d o o pen d r a in outp u ts with 4 0 p u lld o wn, 4 0 pul l u p ? o d t : n o m. val u es of 60 , 1 2 0 or 2 4 0 ? programma b le t e rm i nation a nd driver str e ngth offs e t s ? refresh cycles: 8192 cycles/32 m s ? auto - refresh and se l f - refresh mod e s ? o d t and o u t p ut d r i ve stre n g th a u to - cal i b ration w i th extern a l r e sist o r zq pin ( 2 4 0 ) ? pr o grammab l e io i n terf a ce i n clu d ing o n c h ip t e rm i nation (odt) ? tras l o ck o u t s u pport ? vendor id for device identification ? mirror function with mf pin ? bou n dary sc a n f u nct i on with sen pin ? t w r pro g rammable for writes with auto - precharge ? cal i b rated o u tp u t driv e . act i ve termi n a tion sup p ort ? s hort ras to c a s timing for writes ? o p e rating case temp e r a t u re r a ng e : tc a s e = 0 c to +105c ? packag e : 1 3 6 - ba l l tf bga. ? rohs compliant product www.datasheet.co.kr datasheet pdf - http://www..net/
W641GG2JB 1 - gbit gddr 3 graphics sdram publication release date: apr, 22 , 20 11 - 8 - revision a01 - 002 3. pin configuration 3.1 ballout 1 - cs non - m e rged mode (top view, mf=0) 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 a b c d e f g h j k l m n p r t u v d d q v d d v s s z q v s s q v d d q v s s q v d d q v d d v s s v s s v d d v r e f v s s v d d v d d q v s s q v d d q v s s q v d d q d q 0 d q 1 v s s q v d d q v s s q v d d q d q 2 d q 3 w d q s 0 r d q s 0 d q 4 d m 0 d q 6 d q 5 v s s q d q 7 a 1 a 1 2 a 1 0 a 2 r a r r a s # v s s q d q 2 5 d q 2 4 d q 2 7 d q 2 6 d m 3 w d q s 3 r d q s 3 d q 2 8 d q 2 9 d q 3 0 d q 3 1 v d d v s s s e n v s s q v d d q v s s q v d d q a 3 a 1 1 a 0 v d d q c k e b a 0 c a s # m f v s s v d d v d d q v s s q v s s q v d d q v s s q v d d q c s 0 # b a 1 w e # v d d q a 4 a 7 a 9 v d d q v s s q v d d q v s s q r e s v s s v d d v d d q d q 2 3 d q 2 2 v s s q v d d q v s s q v d d q v d d v s s v d d v s s v r e f v s s v d d v d d q v s s q v d d q d q 9 d q 8 d q 1 1 d q 1 0 r d q s 1 w d q s 1 d q 1 2 d m 1 d q 1 3 d q 1 4 d q 1 5 v s s q b a 2 a 5 c l k # c l k a 6 a 8 / a p d q 1 7 d q 1 9 v s s q d q 1 6 r d q s 2 w d q s 2 d q 2 1 d q 2 0 d m 2 d q 1 8 www.datasheet.co.kr datasheet pdf - http://www..net/
W641GG2JB 1 - gbit gddr 3 graphics sdram publication release date: apr, 22 , 20 11 - 9 - revision a01 - 002 3.2 ballout 2 - cs non - m e rged mode (top view, mf=0) 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 a b c d e f g h j k l m n p r t u v d d q v d d v s s z q v s s q v d d q v s s q v d d q v d d v s s v s s v d d v r e f v s s v d d v d d q v s s q v d d q v s s q v d d q d q 0 d q 1 v s s q v d d q v s s q v d d q d q 2 d q 3 w d q s 0 r d q s 0 d q 4 d m 0 d q 6 d q 5 v s s q d q 7 a 1 r a r a 1 0 a 2 c s 1 # r a s # v s s q d q 2 5 d q 2 4 d q 2 7 d q 2 6 d m 3 w d q s 3 r d q s 3 d q 2 8 d q 2 9 d q 3 0 d q 3 1 v d d v s s s e n v s s q v d d q v s s q v d d q a 3 a 1 1 a 0 v d d q c k e b a 0 c a s # m f v s s v d d v d d q v s s q v s s q v d d q v s s q v d d q c s 0 # b a 1 w e # v d d q a 4 a 7 a 9 v d d q v s s q v d d q v s s q r e s v s s v d d v d d q d q 2 3 d q 2 2 v s s q v d d q v s s q v d d q v d d v s s v d d v s s v r e f v s s v d d v d d q v s s q v d d q d q 9 d q 8 d q 1 1 d q 1 0 r d q s 1 w d q s 1 d q 1 2 d m 1 d q 1 3 d q 1 4 d q 1 5 v s s q b a 2 a 5 c l k # c l k a 6 a 8 / a p d q 1 7 d q 1 9 v s s q d q 1 6 r d q s 2 w d q s 2 d q 2 1 d q 2 0 d m 2 d q 1 8 www.datasheet.co.kr datasheet pdf - http://www..net/
W641GG2JB 1 - gbit gddr 3 graphics sdram publication release date: apr, 22 , 20 11 - 10 - revision a01 - 002 3.3 b a l l o u t m e rg e d mode (top view, mf=0) 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 a b c d e f g h j k l m n p r t u v d d q v d d v s s z q v s s q v d d q v s s q v d d q v d d v s s v s s v d d v r e f v s s v d d v d d q v s s q v d d q v s s q v d d q d q 0 d q 1 v s s q v d d q v s s q v d d q d q 2 d q 3 w d q s 0 r d q s 0 d q 4 d m 0 d q 6 d q 5 v s s q d q 7 a 1 r f u a 1 0 a 2 a 1 2 / c s 1 # r a s # v s s q d q 2 5 d q 2 4 d q 2 7 d q 2 6 d m 3 w d q s 3 r d q s 3 d q 2 8 d q 2 9 d q 3 0 d q 3 1 v d d v s s s e n v s s q v d d q v s s q v d d q a 3 a 1 1 a 0 v d d q c k e b a 0 c a s # m f v s s v d d v d d q v s s q v s s q v d d q v s s q v d d q c s 0 # b a 1 w e # v d d q a 4 a 7 a 9 v d d q v s s q v d d q v s s q r e s v s s v d d v d d q d q 2 3 d q 2 2 v s s q v d d q v s s q v d d q v d d v s s v d d v s s v r e f v s s v d d v d d q v s s q v d d q d q 9 d q 8 d q 1 1 d q 1 0 r d q s 1 w d q s 1 d q 1 2 d m 1 d q 1 3 d q 1 4 d q 1 5 v s s q b a 2 a 5 c l k # c l k a 6 a 8 / a p d q 1 7 d q 1 9 v s s q d q 1 6 r d q s 2 w d q s 2 d q 2 1 d q 2 0 d m 2 d q 1 8 www.datasheet.co.kr datasheet pdf - http://www..net/
W641GG2JB 1 - gbit gddr 3 graphics sdram publication release date: apr, 22 , 20 11 - 11 - revision a01 - 002 4. pin description 4.1 signal description b a ll t y pe det a i le d f u nc tion clk, c l k # input clock: c lk and clk # a r e differential clock inputs. comma n d and add r ess inputs are latched on the r i sing ed g e of clk. all lat e ncies a r e re f erenced to clk. clk and clk # are not inte r nally te r mina t ed. cke in p ut clock en a b le: c k e h i gh a c tiv a tes a n d cke low deactiva t es inter n al clock, device input buff e rs and output d rive r s. t aking c k e l o w provides p r echarge po w er - d own and self r e fresh oper a tions ( a ll banks idle), or active power - down ( row a c tive in a n y ba n k ) . cke is sy n c h r onous for pow e r - d own ent r y a n d exit and f o r self refresh ent r y . cke must b e maintained high th r oughout read, w r ite and b u s snoop bu r s t s. inp u t buffers excluding clk, c lk # and cke are disabled du r ing po w er - d own. input buffers excluding cke a r e disabled du r ing s e lf r e fresh. t he value of cke latched at po w er - u p w i th res going high determines t he termination value of t h e address and command inputs. cs0 #,cs1# input chip select: c h ip select: cs # low e n ables, and cs # hi g h disables the c o mmand decoder. a ll comma n ds except dte r dis are m a sked when cs # is r e g i stered hig h , but internal command execution continues. cs # provides for individual device s e lecti o n on memo r y channels with multiple memo r y d evices. c s # is c o nsidered part of t he c o mmand code. in 1 - cs mode o n ly cs0 # is availa b l e. in 2 - cs mode b o th cs0 # and c s1 # are available, and cs0 # is exclusively used f o r mode r e gister or ext e nded mode r egister prog r amming and s e lf r efresh ent r y . ras # , ca s # , we # input comm a nd input s : c o mmand inp u ts: ras # , cas # and we # ( along with c s0 # o r cs1 # ) define the command to be ent e red. ba0 - ba2 in p ut b a nk add r ess input s : ba0 - b a 2 defi n e to which bank an active, read, w r ite or prec h arge command is bei n g applied. ba0 - b a 2 also dete r mine which mode register or extended mode register is acc e ssed w i th a mode register set comma n d. a0 - a11 (a12) in p ut add r ess in p u t s : add r ess inpu t s: provide t h e r ow address for ac t ive commands and t h e column a d dress and auto precharge func t i on ( a8) for read and wri t e comm a nds, t o select one loc a tion o ut of the m e mory ar r ay in the r es p ective bank. a8 s a mpled d uring a precha r g e command det e rmi n es w hether t h e precharge applies to one bank (a8 low, bank selected by b a0 - ba2) o r all b a nks (a8 h i gh ) . the a ddress inputs also provide the op - code d uring an mode register set c omm a nd. a12 is the msb row a ddress in 1 - cs mode. d q 0 - dq31 i/o data inputs/outpu t s : d a ta input/output: 32 bit da t a bus dm 0 - dm3 in p ut input data masks: inp u t data mask: d m is a n i n put mask signal f o r w r ite data. in p ut data is masked when dm is sampled h i gh along with th a t input data during a w r ite access. dm is s a mpled on the rising and falli n g edges of wdqs. dm0 is associated w i th d q 0 - dq7, dm1 with dq8 - d q 1 5 , dm2 with dq16 - dq23 and dm3 w i th d q 2 4 - dq31. rdqs 0 - rdqs3 output r e a d d a t a str ob es: out p ut with read d ata. rdqs is ed g e - align e d wi t h read d a ta. r d qs0 is associ a ted w i th dq0 - d q 7, rdqs1 with d q 8 - dq15, rdqs2 with dq16 - dq23 and r d qs3 w i th d q 24 - dq31. w dqs 0 - w dqs 3 input wri t e data s t r o bes: wri t e data strobe: input with w r ite d a ta. wdqs is ce n ter - a ligned to the input data. wdqs0 is associated with dq0 - dq7, wdq s 1 w i th d q 8 - dq15, wdqs2 with dq16 - dq23 and w d qs3 with dq24 - dq31. zq r eference odt impedance reference: the zq ball is used to control the odt impedance. www.datasheet.co.kr datasheet pdf - http://www..net/
W641GG2JB 1 - gbit gddr 3 graphics sdram publication release date: apr, 22 , 20 11 - 12 - revision a01 - 002 res in p ut r e set pin : the res pin is a vddq cmos input. res is not internally terminated. when res is at low state the chip goes into full reset. the chip stays in full reset until res goes to high state. the low to high transition of the res signal is used to latc h the cke value to set the value of the termination resistors of the address and command inputs. after exiting the full reset a complete initialization is required since the full reset sets the internal settings to default, including mode register bits. mf i n p u t mirror f u n c t i on : mf is a vddq cmos input. this pin must be hardwired on board either to a power or to a ground plane. with mf set to high, the command and address pins are reassigned in order to allow for an easier routing on board for a back to back memory arrangement. sen i n p ut scan enable : sen is a vd d q c mos input. must be tied to gr o und when n ot in u s e. v ref s u pply r e ference volta g e for command, a d dress a nd data inputs. v dd q s u pply isolated power for t h e inp u t and output buffers . v ssq s u pply isolated gr o und for t h e i np u t and output buffers . v d d s u pply power supply v ss s u pply grou n d rfu r e s e r ved rar r e s e r ved f or alternate rank (see ball o uts) 4.2 addressing 2 - cs mode (cs0#,cs1#) 1 - cs mode (cs0 # ) number of ranks 2 1 row address a0 - a11 a0 - a12 column addresses a2 - a7,a9 a2 - a7,a9 bank address ba0 - ba2 ba0 - ba2 auto precharge a8/ap a8/ap page size 2 kb 2 kb refresh 8k/32 ms 8k/32 ms www.datasheet.co.kr datasheet pdf - http://www..net/
W641GG2JB 1 - gbit gddr 3 graphics sdram publication release date: apr, 22 , 20 11 - 13 - revision a01 - 002 5 . state diagram 5.1 s tate diagram for one activated bank the fol l owi n g d ia g r a m sh o ws a l l possib l e states and transiti o ns for one activated b a nk. the other 37 ba n ks of the grap h ics s d ra m ar e a ss u m e d t o b e i n idl e state. 5.1.1 state diagram for one bank a c t r d s i n g l e b a n k i d l e s e l f r e f r e s h m r s e m r s p r e w r / a r d / a p d e n p d e x p d e n p d e x p o w e r - d o w n a c t i v e p r e c h a r g e a l l b a n k s w r s r e n s r e x a c t i v e a u t o r e f r e s h www.datasheet.co.kr datasheet pdf - http://www..net/
W641GG2JB 1 - gbit gddr 3 graphics sdram publication release date: apr, 22 , 20 11 - 14 - revision a01 - 002 5.1.2 f unction truth table for more than one activated bank if t h ere is more t h an o n e b a nk activated in t h e gr a phics sd r a m, some comman d s c a n be performed i n par a llel due to the c h ip s m u ltiba n k arch i t ecture. the f o llo w ing t a ble defi n es for wh i ch comma n d s such a sch e m e is p o ssibl e . all o t h e r tr a n sitio n s are i l le g a l. notes 1 - 11 d e f i ne the st a rt a nd e nd o f t h e actio n s be l ong i ng to a subm i t ted c o mm a nd. t h is tab l e is b a sed on the assumption t h at t h ere are no o t h e r actio n s on g oing on bank n or b a nk m. if there are a n y actio n s ong o ing on a t h ird b ank t r r d , t rtw a n d t wtr h av e t o b e t a k e n alw a y s i n t o acc o un t. 5.1.2.1 fun c tio n tr u t h t a bl e c u rr e nt st a te o n g o i ng a c t ion o n ba nk n po ss ib l e a c t i on in p a r a l l el on ba nk m a c tive a c tivate 1 act, pre, write, write/a, read, r e ad/ a 2 wr i t e 3 act, pre, write, write/a, read, r e ad/ a 4 wri t e/a act, pre, write, write/a, read 6 read 7) act, pre, write, write/a, read, r e ad/ a 8 read/ a 9) act, pre, write, write/a, read, r e ad/a 8 p r echarg e 10 act, pre, write, write/a, read, r e ad/ a 1 1 p r echarge all 10 - power down entr y 1 2 - idle a c tivate 1) act power down entry 12 - a u to refresh 1 3 - s elf refre s h entry 1 2 - m ode register set (mrs ) 1 4 - extended mrs 14 - extended mrs 2 1 4 - p o we r d o wn p o w er down exi t 1 5 - s elf refre s h s elf refre s h exit 16 - notes : 1. action ac t ivate starts with issuing the c o mmand and en d s after t rc d . 2. during action ac t ivate an act command on ano t her b a nk is allo w ed conside r ing t r rd or t r rd _ rr , a pre command on anoth e r ba n k is allowed any t i me. wr, wr/a, r d and r d/a are always allowed. 3. action wri t e sta r ts w i th issuing the command and ends twr after the first pos. edge of c lk following the last falling wdqs e dge. 4. during action write an a c t or a pre c o mmand on ano t her bank is allowed any time. a new wr or wr/a command on ano t her bank must be s e parated by at least one n o p f r om the ongoing wri t e. rd or rd/a a r e not allo w ed befo r e t w t r or t w tr _ rr is met. 5. action wri t e / a sta r ts with issuing the command and ends twr aft e r the first positive e d ge of clk follo w ing the last falling w dqs e dge. 6. during acti o n w r ite/a an act or a pre command on anoth e r bank is allowed any time. a new wr or w r /a command on a n other bank has to be separa t ed by at le a s t one nop f r om the on g oing comman d . rd is n o t allowed b efore or t wtr or t w tr _ rr is met. rd/a is not allowed during an on g oing wr i te/a action. 7. action read sta r ts w i th issuing the command a nd ends with t he first positive edge of c l k f ollowing the last falling edge of r dq s . 8. during action read and r e a d /a an act or a pre command on ano t her b ank is allowed any time. a new rd or rd/a command on another bank has to be separat e d by a t least one n o p f r om the ong o ing command. a wr or wr/a command on a n other b a nk has to meet t rt w . 9. action read/a sta r ts with issuing the command a n d ends wi t h the first positive edge of clk f o llowing the last falli n g edge of r d q s. 10. action prec h a r g e a n d precharge all start with issuing the command a n d ends after t r p . www.datasheet.co.kr datasheet pdf - http://www..net/
W641GG2JB 1 - gbit gddr 3 graphics sdram publication release date: apr, 22 , 20 11 - 15 - revision a01 - 002 11. during acti o n active an act command on an o ther banks is allo w ed considering t r r d or t rr d _r r . a pre c o mmand on anot h er bank is allowed any t i me. wr, wr/a, r d and r d/a are always allowed. 12. during power down and self r efresh only the exit commands are allowed. 13. auto re f resh s t arts with issuing t he co m mand and ends after t rf c . 14. a c tions mode re g ister set, extended m o de regis t er set a n d ex t ended mode r e gister 2 s e t start with issuing the c o mmand and ends after t mr d . 15. action pow e r down e x it starts with issuing the command and e n ds aft e r t x pn . 16. action self refresh exit sta r ts w i th issuing the command and ends after t x sc . 5.1.3 f unction truth table for cke note s : 1. cken is the l ogic step at cl o ck e d ge n; cken - 1 was t h e state of c ke at t h e previo u s cl o ck e d ge. 2. curre n t st a t e i s the st a t e o f the gd d r3 gra p hics ram imme d iately pri o r to clock e dge n . 3. command is t h e c o mm a nd reg i ster e d a t clock ed g e n, a nd action i s a resu l t of command. 4. all st a t e s a n d sequ e nces not s h own are i l le g a l or r e served. 5. desel or nop c o m m ands should be issued on any c l ock edges occurring during the t xsr p e rio d . a min i m u m o f 1 000 c l ock cyc l e s is r e quir e d b e fore ap p lyi n g a n y o t h e r valid c o mm an d . cke n - 1 cke n current state command action l l power down x stay i n power down self ref r esh x stay in self ref r esh l h power down desel or nop exit power down self ref r esh desel or nop exit self refresh 5 h l all banks idle desel or n o p entry precharge power down bank(s) active desel or nop entry active power down all banks i d le auto refresh entry s e lf r e fresh www.datasheet.co.kr datasheet pdf - http://www..net/
W641GG2JB 1 - gbit gddr 3 graphics sdram publication release date: apr, 22 , 20 11 - 16 - revision a01 - 002 5.2 f u nctio n al block diagram in 1 - cs mo d e a d d r e s s b u f f e r a 0 - a 7 , a 9 , a 8 / a p , a 1 0 - a 1 1 , a 1 2 b a 0 - b a 2 a 8 / a p r e f r e s h c o u n t e r r o w a d d r e s s e s a 0 - a 1 2 , b a 0 - b a 2 c o l u m n a d d r e s s e s a 2 - a 7 , a 9 c o l u m n a d d r e s s b u f f e r r o w a d d r e s s b u f f e r r o w d e c o d e r m e m o r y b a n k 4 m e m o r y b a n k 5 m e m o r y b a n k 6 m e m o r y b a n k 7 r o w d e c o d e r r o w d e c o d e r r o w d e c o d e r d l l o u t p u t b u f f e r s i n p u t b u f f e r s c k e c l k / c l k d q 0 - d q 7 d q 8 - d q 1 5 d q 1 6 - d q 2 3 d q 2 4 - d q 3 1 z q m f r e s / w e / c a s / r a s / c s 0 m e m o r y a r r a y b a c k 0 8 1 9 2 x 5 1 2 x 3 2 b i t m e m o r y a r r a y b a c k 1 8 1 9 2 x 5 1 2 x 3 2 b i t m e m o r y a r r a y b a c k 2 8 1 9 2 x 5 1 2 x 3 2 b i t m e m o r y a r r a y b a c k 3 8 1 9 2 x 5 1 2 x 3 2 b i t m o d e r e g i s t e r c o n t r o l l o g i c & t i m i n g g e n e r a t o r s e n s e a m p l i f i e r s a n d d a t a b u s b u f f e r s e n s e a m p l i f i e r s a n d d a t a b u s b u f f e r s e n s e a m p l i f i e r s a n d d a t a b u s b u f f e r s e n s e a m p l i f i e r s a n d d a t a b u s b u f f e r c o l u m n d e c o d e r c o l u m n d e c o d e r c o l u m n d e c o d e r c o l u m n d e c o d e r d q 0 - d q 7 r d q s 0 w d q s 0 d m 0 d q 8 - d q 1 5 r d q s 1 w d q s 1 d m 1 d q 1 6 - d q 2 3 r d q s 2 w d q s 2 d m 2 d q 2 4 - d q 3 1 r d q s 3 w d q s 3 d m 3 www.datasheet.co.kr datasheet pdf - http://www..net/
W641GG2JB 1 - gbit gddr 3 graphics sdram publication release date: apr, 22 , 20 11 - 17 - revision a01 - 002 5.3 functional block diagram in 2 - cs mode a d d r e s s b u f f e r a 0 - a 7 , a 9 , a 8 / a p , a 1 0 - a 1 1 b a 0 - b a 2 a 8 / a p r e f r e s h c o u n t e r r o w a d d r e s s e s a 0 - a 1 1 , b a 0 - b a 2 c o l u m n a d d r e s s e s a 2 - a 7 , a 9 c o l u m n a d d r e s s b u f f e r r o w a d d r e s s b u f f e r r o w d e c o d e r m e m o r y b a n k 4 m e m o r y b a n k 5 m e m o r y b a n k 6 m e m o r y b a n k 7 r o w d e c o d e r r o w d e c o d e r r o w d e c o d e r d l l o u t p u t b u f f e r s i n p u t b u f f e r s c k e c l k / c l k d q 0 - d q 7 d q 8 - d q 1 5 d q 1 6 - d q 2 3 d q 2 4 - d q 3 1 z q m f r e s / w e / c a s / r a s / c s 0 m e m o r y a r r a y b a c k 0 4 0 9 6 x 5 1 2 x 3 2 b i t m e m o r y a r r a y b a c k 1 4 0 9 6 x 5 1 2 x 3 2 b i t m e m o r y a r r a y b a c k 2 4 0 9 6 x 5 1 2 x 3 2 b i t m e m o r y a r r a y b a c k 3 4 0 9 6 x 5 1 2 x 3 2 b i t m o d e r e g i s t e r c o n t r o l l o g i c & t i m i n g g e n e r a t o r s e n s e a m p l i f i e r s a n d d a t a b u s b u f f e r s e n s e a m p l i f i e r s a n d d a t a b u s b u f f e r s e n s e a m p l i f i e r s a n d d a t a b u s b u f f e r s e n s e a m p l i f i e r s a n d d a t a b u s b u f f e r c o l u m n d e c o d e r c o l u m n d e c o d e r c o l u m n d e c o d e r c o l u m n d e c o d e r d q 0 - d q 7 r d q s 0 w d q s 0 d m 0 d q 8 - d q 1 5 r d q s 1 w d q s 1 d m 1 d q 1 6 - d q 2 3 r d q s 2 w d q s 2 d m 2 d q 2 4 - d q 3 1 r d q s 3 w d q s 3 d m 3 / c s 1 b a n k 0 b a n k 1 www.datasheet.co.kr datasheet pdf - http://www..net/
W641GG2JB 1 - gbit gddr 3 graphics sdram publication release date: apr, 22 , 20 11 - 18 - revision a01 - 002 6. f unctional description th i s section d e scribe the u n itization se q ue n ce o f the g d ram. it has be e n divi d ed in to parts for e a ch o f the o p erations mod e s ( 1 - cs or 2 - cs). in the i n it i a l i z a t i on, a n d b e f o re the c h oice of the o perati o n m ode by m o de r egistration set command, the defau l t mode is 1 - cs t h is impli e s a common i n itial i zat i on seq u ence up to po i nt 7 . 6 .1 system configurations figure shows typical system configurations for 1 - cs mode and 2 - cs mode. 2 - cs mode is equivalent to a clamshell configuration with two 512mbit device s (rank 0 and rank 1) sharing a common interface; it benefits from the single physical pin load of this monolithic solution. in 1 - cs mode the device is addressed as a single 8 - bank device, and the msb row address a12 selects between the upper and lower half of the die. 6.1.1 system configurations in 1 - cs mode and 2 - cs mode 1 - c s m o d e 2 - c s m o d e c o n t r o l l e r 1 g b i t g d d r 3 s d r a m 5 1 2 m b i t g d d r 3 s d r a m ( r a n k 0 ) 5 1 2 m b i t g d d r 3 s d r a m ( r a n k 1 ) 1 g b i t g d d r 3 s d r a m c o n t r o l l e r c s 0 # c l k , c l k # a d d r / c m d d q 0 - d q 3 1 d m 0 - d m 3 w d q s 0 - w d q s 3 r d q s 0 - r d q s 3 c l k , c l k # a d d r / c m d d q 0 - d q 3 1 d m 0 - d m 3 w d q s 0 - w d q s 3 r d q s 0 - r d q s 3 c s 0 # c s 1 # www.datasheet.co.kr datasheet pdf - http://www..net/
W641GG2JB 1 - gbit gddr 3 graphics sdram publication release date: apr, 22 , 20 11 - 19 - revision a01 - 002 6.1. 2 initialization in 1 C cs mode the gddr3 graphics sdram must be p o wered up a nd i n itial i zed in a pr e defin e d man n er. op e rat i on a l proc e dures oth e r t h an those s p ecified m a y result in un d ef i ned oper a t i on or p e rman e nt damage to t h e d e vice.the f o llo w ing s e qu e nce is h igh l y r e com m ended for power - up: 1. app l y p o wer ( v d d , v dd q , v ref ). apply v dd b e f o r e o r a t t h e sam e tim e a s v d d q , app l y v d d q b e f o re o r a t t h e same time as v ref . mainta i n res = l o w and cs0 = h igh to ens u r e th a t all the dq outputs will b e in hiz state, a ll active term i natio n s o f f and the d l l off. a l l o t h e r p ins may b e un d ef i ne d . 2. mainta i n sta b le con d it i ons f o r 2 0 0 s m i nimum f o r the gddr3 to pow e r u p . 3. after cl o ck is st a b l e , s e t cke to h igh or lo w . after t ats min i m u m set res to hi g h . on t h e risi n g e d ge of res, the c k e v a lue is l a tc h ed to d e t e rm i ne t h e a ddress and command b u s t e rm i na t ion va l ue. if cke i s samp l ed low the a d dress termin a t i on val u e i s set to zq / 2 . if cke i s samp l ed high, t h e addr e s s a n d c o mm a nd bus terminati o n i s set to z q . 4. after t ath minimum, set c k e to high. 5. wa i t a min i m u m of 700 cycles to c a libr a te a n d up d ate the a ddress and comma n d termi n a tion imp e danc e s. i s s u e deselect on the comma n d bus duri n g t h ese 700 cycles. 6. app l y a precharge a l l c o mm a nd by hol d ing cs0 l o w and w a it for t rp t o e x pir e . 7. iss u e an ext e nded mode re g ist e r set comm a nd to set t h e mo d e to 1 - c s and activate the dll. the m o de s e lection will be do n e using the b a nk a ddr e s s ba2 t h at w i ll be set to l o w l e vel for 1 - cs mo d e (in dual r a nk m o de). 8. iss u e a n m o de re g ist e r set command after t mrd is met to reset the d l l and d e f i ne the op e r a t i ng par a m e t e r s. 9. wa i t 10 0 0 cycl e s of cl o c k in p u t to l o ck the dll. n o r e ad c o mm a nd c a n b e a pp l ied duri n g th i s time. since the imped a nce cali b ration is alr e ady complete d , the dll mimic circuitry c a n u se t h e a ct u al progr a m m e d d river imped a nce val u e. 10. iss u e a precharge all comma n d to each o f the p rogrammed r a nks or issue si n g le bank p r e charge c o mm a nds to each of the 8 b a nks to p l ace t h e c h ip in an i d le state. 11. iss u e or more auto refresh comman d s. www.datasheet.co.kr datasheet pdf - http://www..net/
W641GG2JB 1 - gbit gddr 3 graphics sdram publication release date: apr, 22 , 20 11 - 20 - revision a01 - 002 6.1. 3 initialization in 2 C cs mode the gddr3 graphics sdram must b e p o wered up a nd i n itia l i z ed i n a p redefi n ed ma n ner. o p e r atio n a l p r o cedur e s other than th o se sp e c i f i ed may r e sult in und e f i ned op e r a t i on o r perman e nt dama g e to the devic e . the fo l low i ng s e que n ce is h igh l y r e com m ended for power - up: 1. app l y p o wer ( v d d , v dd q , v ref ). apply v dd b e f o r e o r a t t h e sam e tim e a s v d d q , app l y v d d q b e f o re o r a t t h e same time as v ref . mainta i n res = l o w and cs0 = h igh to ens u r e th a t all the dq outputs will b e in hiz state, a ll active term i natio n s o f f and the d l l off. a l l o t h e r p ins may b e un d ef i ne d . 2. mainta i n sta b le con d it i ons f o r 2 00 s m i nimum f o r the gddr3 to pow e r u p . 3. after cl o ck is st a b l e , s e t cke to h igh or lo w . after t ats min i m u m set res to hi g h . on t h e risi n g e d ge of res, the c k e v a lue is l a tc h ed to d e t e rm i ne t h e a ddress and command b u s t e rm i na t ion va l ue. if cke i s samp l ed low the a d dress termin a t i on val u e i s set to zq / 2 . if cke i s samp l ed high, t h e addr e s s a n d c o mm a nd bus terminati o n i s set to zq 4. after ta t h m i nimum, s e t cke to h i gh. 5. wa i t a min i m u m of 700 cycles to c a libr a te a n d up d ate the a ddress and comma n d termi n a tion imp e danc e s. i s s u e deselect on the comma n d bus duri n g t h ese 700 cycles. 6. app l y a precharge a l l c o mm a nd by hol d ing cs0 l o w and w a it for t rp t o e x pir e . 7. iss u e an ext e nded mode re g ist e r set comm a nd to set t h e mo d e to 2 - c s and activate the dll. the m o de s e lection will be do n e using the b a nk a ddr e s s ba2 t h at w i ll be set to h i gh lev e l for 2 - cs mode (in si n g le ra n k mo d e ). 8. iss u e a n m o de re g ist e r set command after t mrd is met to reset the d l l and d e f i ne the op e r a t i ng par a m e t e r s. 9. wa i t 10 0 0 cycl e s of cl o c k in p u t to l o ck the dll. n o r e ad c o mm a nd c a n b e a pp l ied duri n g th i s time. since the imped a nce cali b ration is alr e ady complete d , the dll mimic circuitry c a n u se t h e a ct u al progr a m m e d d river imped a nce val u e. 10. iss u e a precharge all comma n d to each o f the p rogrammed r a nks or issue si n g le bank p r e charge c o mm a nds to each of the 1 6 b anks in 2 - cs mode, to p lace the chip in a n idle state. 11. iss u e or more auto refresh comman d s. www.datasheet.co.kr datasheet pdf - http://www..net/
W641GG2JB 1 - gbit gddr 3 graphics sdram publication release date: apr, 22 , 20 11 - 21 - revision a01 - 002 6.1. 3.1 power up sequence v d d v d d q v r e f r e s c k e c k e # c l k c o m d m a 8 b a 0 , b a 1 r d q s w d q s d q a c t r a r a r a a r f a r f p a m r s e m r c o d e c o d e c o d e c o d e p a d e s d e s a l l b a n k s a l l b a n k s b a 0 = h , b a 1 = l b a 0 = l , b a 1 = l t r p t m r d t m r d t r p t r f c t r f c 7 0 0 c y c l e s m r s : m r s c o m m a n d w i t h d l l r e s e t e m r : e m r s c o m m a n d d e s : d e s e l e c t 1 0 0 0 c y c l e s p a : p r e a l l c o m m a n d a r f : a u t o r e f r e s h c o m m a n d a . c . : a n y c o m m a n d d o n t c a r e m i n . 2 0 0 u s v d d a n d c l k s t a b l e t a t s t a t h www.datasheet.co.kr datasheet pdf - http://www..net/
W641GG2JB 1 - gbit gddr 3 graphics sdram publication release date: apr, 22 , 20 11 - 22 - revision a01 - 002 .2 m irror function t h e gddr3 graphics sdram p rovid e s a mirror fu n ct i on (mf) pin to cha n ge t h e p h ys i cal l o cation of the c o mm a nd a n d address pins as s i sting in routing devices back to back. the m f ball should be tied direc t ly to vssq or vddq de p en d ing on the control l ine orie n t ati o n d e sired. the p i ns affected b y t h is mirror f u nction m o de a re listed in t a b le . the cs1# and a12 p ins are not aff e cted b y mirror f u nct i on. 6.2.1 ball assignment with mirror function signal signal signal signal ball mf=0 mf=1 ball mf=0 mf=1 ball mf=0 mf=1 ball mf=0 mf=1 f4 cas# cs0# h3 ras# ba2 k2 a10 a8/ap k11 a8/ap a10 f9 cs0# cas# h4 cke we# k3 a2 a6 l4 a11 a7 g4 ba0 ba1 h9 we# cke k4 a0 a4 l9 a7 a11 g9 ba1 ba0 h10 ba2 ras# k9 a4 a0 m4 a3 a9 h2 a1 a5 h11 a5 a1 k10 a6 a2 m9 a9 a3 www.datasheet.co.kr datasheet pdf - http://www..net/
W641GG2JB 1 - gbit gddr 3 graphics sdram publication release date: apr, 22 , 20 11 - 23 - revision a01 - 002 6. 3 commands in t h e foll o wing t a ble cken refers to the positive edge of clk c o rr e spon d ing to t h e cl o c k cycle wh e n the c o mma n d is given to the grap h ics s d ram. cken - 1 refers to the pr e vious p o s i t i ve e dge o f clk. f o r a l l comm a nd a n d addr e s s i n puts c ken i s impli e d. a l l inp u t stat e s o r se q uenc e s n o t sh o wn are ill e gal o r reserve d . 6. 3 .1 c o m ma n d o v e rv i ew f or 1 - cs m od e o p erati o n co d e cke n - 1 cke n c s0 # r as # c as # w e # ba0 ba1 ba2 a8 a2 - 7 a 9 - 1 1/12 note device delselect desel h h h l x h x x h x l h x x x x x 1 data termi n a tor d i sable dterdis h h h h l h x x x x x 1 , 2 no op e ration nop h h l h h h x x x x x m o d e r e g is t e r s e t mrs h h l l l l 0 0 0 opc o de exte n ded mode r egister set emrs h h l l l l 1 0 opcode exte n ded mode r egister set 2 emrs2 h h l l l l 0 1 0 opcode b a nk a c tivate act h h l l h h ba ba ba row ad r e ss 1 , 3 read rd h h l h l h ba ba ba l col. read w/ aut o prech a rge rd/a h h l h l h ba ba ba h co l . w rite w r h h l h l l ba ba ba l c o l . 1 , 4 write w/ auto p r e charge w r /a h h l h l l ba ba ba h co l . pr e charge pre h h l l h l ba ba ba l x 1 , 4 pr e charge all preall h h l l h l x x x h x a u t o r e fr e s h a ref h h l l l h x x x x x 1 , 5 p o we r dow n mo d e e n try p w d nen h l h l x h x h x h x x x x x 1 , 6 p o wer down mo d e ex i t pw d nex l h x x x x x x x x x 1 , 7 s e lf r e fr e s h e n try srefen h l l l l h x x x x x 1 , 8 s e lf r e fr e s h exit srefex l h x x x x x x x x x 1 , 9 notes : 1. x rep r ese n ts D dont car e . 2. this c o mmand is invoked w hen a read is issued on anot h er d ram r a n k placed o n the same co m mand bus. c annot be in powe r - do w n or s e lf - refr e sh state. t he read command will cause the data termination to be disabled. 3. ba0 - ba2 p r ovide bank add r ess, a0 - a11, a12 provide the r ow add r ess. 4. ba0 - ba2 p r ovide bank add r ess, a2 - a7, a9 provide the column address, a8/ap cont r ols auto p r ech a rge. 5. auto ref r esh and self refresh ent r y differ only by the state of cke. 6. pw d nen is select e d by issuing a d e sel or nop at the fir s t positive clk edge f o llowing the high to low t r ansition of cke. 7. first possible valid c o mmand after t x pn . during t x p n only n o p or desel c o mmands are al l o wed. 8. self r efresh is select e d by issuing aref at the first positive clk edge f o llowing the high to low t r ansition of cke. 9. first possible valid c o mmand after t x sc . during t x s c only n o p or desel c o mmands are al l o wed. www.datasheet.co.kr datasheet pdf - http://www..net/
W641GG2JB 1 - gbit gddr 3 graphics sdram publication release date: apr, 22 , 20 11 - 24 - revision a01 - 002 6. 3 .2 c o m ma n d o v e rv i ew f or 2 - cs m od e o p erati o n c o de ra n ks cke n - 1 cke cs0 # cs1 # r a s # c a s # w e # ba0 ba1 ba2 a8 a2 - 7 a9 - 1 1 note device deselect desel h h h h l x h x x h x l h x x x x x 1 data te rminator disable d t erd i s h h h h h l h x x x x x 1 , 2 no op e ration nop h h l x x l h h h x x x x x m o de re g ist e r set mrs h h l x l l l 0 0 0 opcode exte n ded mode r egister set em r s h h l x l l l 1 0 opco d e exte n ded mo d e register set 2 em r s2 h h l x l l l 0 1 0 opcode b a nk activate act memblock 1 h h l h l h h b a ba ba row address 1 , 3 memblock 2 h h h l l h h ba ba ba row address read rd memblock 1 h h l h h l h ba ba ba l col. 1 , 4 memblock 2 h h h l h l h b a ba ba l col. read w/ aut o prech a rge rd/a memblock 1 h h l h h l h b a ba ba h col. 1 , 4 memblock 2 h h h l h l h b a ba ba h col. write w r memblock 1 h h l h h l l b a ba ba l col. 1 , 4 memblock 2 h h h l h l l b a ba ba l col. write w/ auto p r e charge wr/a memblock 1 h h l h h l l ba ba ba h col. 1 , 4 memblock 2 h h h l h l l b a ba ba h col. pr e charge pre memblock 1 h h l h l h l b a ba ba l x 1 memblock 2 h h h l l h l b a ba ba l x b o th h h l l l h l b a ba ba l x pr e charge all preall memblock 1 h h l h l h l x x x h x 1 memblock 2 h h h l l h l x x x h x b o th h h l l l h l x x x h x a u to r e fr e s h aref memblock 1 h h l h l l h x x x x x 1 , 5 memblock 2 h h h l l l h x x x x x both h h l l l l h x x x x x p o wer down mo d e e n try pwdnen h l h x l h l x x h x h x h x x x x x 1 , 6 p o wer down mo d e ex i t pwdnex l h x x x x x x x x x x 1 , 7 s e lf r e fr e s h e n try srefen h l l l l l h x x x x x 1 , 8 s e lf refre s h exit srefex l h x x x x x x x x x x 1 , 9 www.datasheet.co.kr datasheet pdf - http://www..net/
W641GG2JB 1 - gbit gddr 3 graphics sdram publication release date: apr, 22 , 20 11 - 25 - revision a01 - 002 notes : 1. x rep r ese n ts D dont car e . 2. this c o mmand is invoked w hen a read is issued on anot h er d ram r a n k placed o n the same co m mand bus. c annot be in powe r - do w n or s e lf - refr e sh state. t he read command will cause the data termination to be disabled. refer to figu r e (self calibration of pmos and nmos legs) for t i ming. 3. ba0 - ba2 p r ovide bank add r ess, a0 - a11, a12 provide the r ow add r ess. 4. ba0 - ba2 p r ovide bank add r ess, a2 - a7, a9 provide the column address, a8/ap cont r ols auto p r ech a rge. 5. auto ref r esh and self refresh ent r y differ only by the state of cke. 6. pw d nen is select e d by issuing a d e sel or nop at the fir s t positive clk edge f o llowing the high to low t r ansition of cke. 7. first possible valid c o mmand after t x pn . during t x p n only n o p or desel c o mmands are al l o wed. 8. self r efresh is select e d by issuing aref at the first positive clk edge f o llowing the high to low t r ansition of cke. 9. first possible valid c o mmand after t x sc . during t x s c only n o p or desel c o mmands are al l o wed. 6. 3 .3 description of command com m and des c ription desel t he d e sel functi o n p revents new comman d s from b e ing e xecuted by t h e gra p hics sdram. t h e gra p hics sdram i s effect i vely dese l ected. oper a t i ons in pro g r e ss a r e n o t affected. nop t he n o p comm a nd is used to perform a n o oper a t i o n to the graph i cs sdram, w h ich is selected (c o rrespo n ding cs is low). t h is preve n ts u n wanted comman d s f r om bei n g r e gistered d u ring i d le or wait st a t es. op e rations alr e ady in pro g ress a r e n o t a f fected. mrs t he mo d e reg i st e r is lo a ded via a ddress in p u ts a0 - a 1 1. f o r m o re d e tails see mo d e reg i s ter set co m m a nd (m r s ) . the mrs c o mm a nd can on l y b e issued w h en all b anks are id l e and no b u rsts are in pro g ress. a s u bseq u ent executab l e comm a nd can n ot b e i ssued u n t i l t mrd is m e t. emrs the exten d ed mode r e gister is l oad e d via ad d ress i npu t s a0 - a11. f o r more d e ta i ls s e e s e ct i on exten d ed m o d e re g i st e r c o mm a nd s em r s 1 - 3 . the emrs c o mma n ds can on l y be i s s u ed wh e n all b a nks are idle a n d n o b u rsts are in progr e ss. a subs e que n t executa b le comm a nd cann o t be issu e d u n t i l t mrd is m e t. a c t t he act c o mm a nd i s used to o pen (or activate) a r o w in a particu l a r b a nk f o r a su b s e qu e nt access. the value on the ba0 - ba2 in p u ts se l e cts the ba n k, and the a d dress provi d ed in i n puts a0 - a11/a12 sel e cts t h e r o w. th i s row remai n s active (or o p en) f o r accesses until a prech a r g e (pre, r d/a, o r w r /a c o mm a nd) is issu e d to t h at b a nk. a prech a rge must be i s s u ed befo r e o p en i ng a different r o w in t h e s a me b ank. rd the r d c o mma n d is u sed to i n itiate a burst r e ad access to a n act i ve r o w. the val u e o n t h e ba0 - ba2 inp u ts selects the b ank, a nd the ad d ress p r o vided o n inp u ts a2 - a7, a9 se l e cts the col u mn l o catio n . t h e row will remain o p en for s u bseq u ent a ccesses. f o r r d c o mma n ds the v a lue on a8 is set l o w . rd/a t he r d /a comm a nd is u sed to i n it i a te a b u rst read access to an active row. the val u e o n the ba0 - ba2 in p u ts selects the b a nk, a n d the a ddress provid e d on in p u ts a2 - a7, a9 se l e cts t h e c o lumn loc a t i on. the val u e o n inp u t a8 i s set hig h . the row be i ng accessed will be pr e c h a rged at the e n d o f t h e re a d b u rst. the same ind i vidu a l - ba n k pr e c h a rge function i s p e rf o r med l ike it i s d e s c r i bed for the pre comman d . auto prech a rge ensur e s that t h e prechar g e is i n itiated a t t h e earl i est va l id st a ge within the b u rst. t h e us e r must n o t i s s u e a n e w act comm a nd to t h e same bank until the prec h a rge time ( t r p ) is c o m p lete d . t h is time is d e t e rm i ned as if an exp l icit pre comma n d was issued at t h e earli e st poss i b le time as describ e d in sect i on Dreads (rd) . www.datasheet.co.kr datasheet pdf - http://www..net/
W641GG2JB 1 - gbit gddr 3 graphics sdram publication release date: apr, 22 , 20 11 - 26 - revision a01 - 002 wr the w r comma n d i s us e d to initi a te a burst wr i t e access to an active row. the val u e o n the ba0 - ba2 in p u ts selects the b ank, a nd the ad d ress p r o vided o n inp u ts a2 - a7, a9 se l e cts the col u mn l o catio n . t h e row will remain o p en for s u bseq u ent a ccesses. f o r w r comm a nds t h e value o n a8 i s set lo w . i n put d a ta app e aring o n t h e d q s is written to the memory a r r a y d e pe n ding o n t h e v a lue on the dm in p u t ap p eari n g c o inci d ent with the d a ta. if a g i v e n dm si g nal is reg i ster e d lo w , the corresp o ndi n g data wi l l b e writt e n to the memory; if the dm sig n al is re g ist e red high, the c o rrespo n ding d a ta in p u ts wi l l be i g nore d , and a write w ill n o t be ex e c u t e d f o r that byte / column l o cat i on. w r/a th e wr/a c o mm a nd is u s ed t o i n iti a te a bu rst wri t e acc e ss to an active row. the va l ue on the ba0, ba1 a nd ba2 i np u ts selects the b ank, a nd the ad d ress p r o vided o n inp u ts a2 - a7, a9 s e lects the col u mn l o catio n . t h e value o n inp u t a8 is set hig h . t h e r o w bei n g accessed wi l l be prech a rged at t h e end of t h e w r i t e b u rst. the same ind i vidu a l - ba n k p r e charge functi o n i s p e rf o rm e d which is descri b ed for the pre command. auto prech a r g e ensur e s that t h e p r echar g e is i n itiated a t t h e earl i est va l id st a ge within the b u rst. t h e us e r is n o t all o wed to issue a new act to the same ba n k u n t i l t h e p rechar g e time ( t r p ) is complete d . t h is time is determin e d as i f an ex p licit pre comma n d w a s i ssued at t h e e a rli e st poss i ble time as d e scrib e d i n sect i on Dwrites (wr ) . i n put d a ta app e aring o n t h e d q s is written to the memory a r r a y d e pe n ding o n t h e d m i n put l og i c l e vel ap p eari n g c o inci d ent with the d a ta. if a g i v e n dm si g nal is reg i ster e d lo w , the corresp o ndi n g data wi l l b e writt e n to the memory; if the dm sig n al is re g ist e red high, the c o rrespo n ding d a ta in p u ts wi l l be i g nore d , and a write w ill n o t be ex e c u t e d to that byte / column l o cation. p r e t he pre command i s us e d to d e act i vate the o pen row in a p a rt i c u lar ba n k. t h e bank wi l l be ava i lab l e for a subse q uent row access a s p ecified time ( t r p ) aft e r the pre c o mm a nd is issue d . i n puts ba0 - ba2 s e lect the ba n k to be pr e charg e d. a8/ap is s e t to low. once a b a nk has be e n prech a rged, it i s i n t h e idle state and m u st be act i vated a ga i n pr i o r to a n y rd or w r c o mma n ds b e ing issu e d to th a t ba n k. a pre command wi l l b e treated as a n o p if there i s no o pen row in that ba n k, or if the p r ev i ously op e n row is a lrea d y i n the p r o cess o f prech a r g in g . p r ea l l the preall c o mma n d is us e d to de a ct i v a t e all open rows in the memory devic e . the b anks w i ll be avai l ab l e f o r a subs e que n t row access a sp e cif i ed t i me ( t rp ) after the preall command i s issu e d . once t h e b anks have be e n p rechar g ed, th e y are i n the i d le state a nd must b e a ct i v a t e d prior to a n y r e ad or write c o mm a nds be i ng issue d . t h e preall comm a nd wi l l be tr e a ted as a n o p f o r those b anks where there is no o p en row, or i f a previ o usly op e n row is alr e ady in the p r o cess of p re c harg i ng. preall is issu e d by a pre comm a nd w i th a 8 /ap set to hi g h. a r ef the aref is u s e d d u ring n o rmal o p eration of the gdd r 3 graph i cs ram to refresh the memory co n t e n t. t h e refr e sh a ddr e s s i ng is gen e rated by t h e i n ternal refre s h co n t ro l ler. t h is makes t h e addr e ss b i ts Ddon t car e during an aref command. the gddr3 graphics sdram requires aref cycles at an average periodic interval of t r e f i (m a x). to im p r o ve effic i ency a max i m u m n u m b er of e i ght a r ef c o mm a nds can be p o sted to one memory device (w i t h t rfc from aref to aref) as described in section Dauto r e fre s h comm a nd (aref) . t h is m e ans t h at the maximum abs o lute interval b e tw e en any aref command is 8 x t ref i (max). this m a ximum a b sol u te i n t e rval is to a l low the g d dr3 gra p hics ram o u t p ut d r i vers a nd intern a l t e rm i nators to recal i brate, comp e n sating for voltage a nd temperature ch a nges. all ba n ks must b e i n t h e i d le state before issui n g the aref c o mm a nd. t h e y wi l l be simulta n eous l y r e fresh e d a nd return to the i d le state a f ter aref is completed. t r f c is t h e m i nimum requ i red t i me b e tween a n a r ef comm a nd a n d a fo l low i ng act/aref comm a nd. www.datasheet.co.kr datasheet pdf - http://www..net/
W641GG2JB 1 - gbit gddr 3 graphics sdram publication release date: apr, 22 , 20 11 - 27 - revision a01 - 002 s r efen the self r e fr e sh f u nct i on can b e used to retain data in the gddr3 grap h ics r am ev e n if the r e st of t h e system is p o wer e d dow n . w h en enteri n g t h e s e lf r e fr e s h m od e by i ssuing the sre f en c o mma n d, the gddr3 gra p hics ram reta i n s d a ta w ithout external cl o c k i ng. the srefen c o mm a nd is initiated l ike an aref comm a nd e x c e pt c ke i s disa b led (low). t h e dll is au t omatica l ly dis a bled upon en t eri n g self refresh mo d e and a u t o m a t i cally en a bl e d and reset up o n e xiting self refresh. ( 1 000 cycles must then o c c u r b e f o re a r d o r dter d i s comm a nd can be issu e d ) t h e active terminati o ns rem a in en a bled d u ring se l f refresh. in p u t si g nals except cke a re Ddon t car e . if two gd d r3 gra p hics r a ms s h are t h e same command a nd addr e s s b u s, self refresh may b e entered o n ly for the two devic e s at the sa m e time. i n 2 - cs mode, both memories may only enter self - refresh, i n para l lel. s r efex the srefex c o mma n d is u sed to e xit the self ref r esh mode. t h e dll is automatica l ly e na b led a n d r e set up o n e xiting. the p roced u re for exi t i n g s e lf r e fresh re q u ires a seq u ence of comm a nds. first c l k a nd clk # m u st be stab l e p rior to cke go i ng fr o m low to high. once cke is h i gh, the gddr3 gr a ph i cs ram m u st receive only nop/desel c o m m ands until t xsc is satisf i ed. th i s time is r e qu i r e d f o r the comp l e t i on of any intern a l r e fresh i n progress. a simp l e a lg o r i t h m f o r m e eting b o th refresh, d ll req u irements and o u t p ut calibration is to apply nops for 1000 cycles before applying any other command to allow t h e dll to lock and t h e output drivers to rec a libr a te. p w dnen t he p w dnen command e n abl e s the p o wer down mo d e . it is e n ter e d when cke is set l o w to g e ther with a nop/desel. the cke signal is sa m p l e d at the rising edge of the clock. once t h e power down m o de is initi a t e d, a l l o f the receiv e r circu i ts except clk a nd cke a re g a ted off to r e duce p o wer c o nsumptio n . t h e dll remains active (un l ess d isab l ed before w i th emrs). all banks c a n be set to id l e state or st a y active. duri n g power d o wn mo d e , r e fresh op e r a t i ons ca n not be p e rform e d; t h erefore the r e fresh cond i t i ons of the c h ip h a ve to be considered and if nece s sary p o wer down state has to be left to perfo r m an auto refresh cycle. if two gd d r3 grap h ics rams s h are the same command a n d a dd ress b u s, power down may b e e n tered on l y for the two devices at the same time. p w dnex a cke high va l ue s a m p led at a low to h igh tr a n sition of c l k is re q u ired to e xit po w er d o wn m o de. once cke is h i gh, the gddr3 gr a phics ram must r e c e ive on l y nop/desel comman d s u n t i l t xpn is satisfied. after t xpn any command can be i ss u ed, but i t h a s to comply with t h e state in w h ich t h e pow e r d o wn mode was e n t e r e d. dterdis data t e rmi n ation d i s a ble (bus sno o ping for rd comm a nds): t h e d a ta t e rminati o n disab l e command is detected by the d e vice by sno o pi n g t h e bus for rd commands excl u d i n g c s . the gddr3 grap h ics r am w i ll disa b le i t s data termin a tors w hen a rd command is d e t e c t e d . the t e rm i nators are dis a bled start i ng a t cl - 1 clocks after the rd com m and is detected and the durat i on is 4 clocks. in a 2cs system, both dram devices will s n oop the b u s f o r r d c o mm a nds to either d e vice a n d both wi l l dis a ble the i r termi n a t o rs i f a rd c o mma n d is d e tected. the command a nd ad d ress termin a t o rs are a lways en a ble d . see f i g u r e (odt disable timing during a read command) f o r an e xample of when the d a ta termin a t o rs are d isabl e d duri n g a rd c o mm a nd. www.datasheet.co.kr datasheet pdf - http://www..net/
W641GG2JB 1 - gbit gddr 3 graphics sdram publication release date: apr, 22 , 20 11 - 28 - revision a01 - 002 6. 3 .4 minimum delay f r om rd/a and wr/a to any other command (to another bank) with concurre n t ap fr om co m m a nd t o co m m and m i n i m u m d e l a y t o an ot h e r ba nk (w ith c o n c ur r ent a u t o pr e c h ar g e) note wr/a rd or rd/a (wl + 2) t c k + t wtr w r o r w r /a 2 t ck pre t ck act t ck rd/a rd or rd/a 2 t ck wr or w r /a (cl + 4 - w l ) t ck pre t ck act t ck 6. 4 boundary scan 6. 4 .1 general description the 1 - gbit gdd r 3 i n corp o r a t e s a modifi e d b ou n dary scan test mo d e . t h is m o de does n t o p erate in accorda n ce w ith ieee sta n dard 1 1 49.1 - 19 9 0. to s a ve the curre n t g d dr3 bal l - out, this m o de will scan the pa r a l lel d a ta i n put a nd output t h e sca n ned data t h rough the w dqs0 p i n c o ntroll e d by sen. note: both pads cs1 # a nd a12 wi l l b e act i vated and co u ld be acc e ss e d duri n g b o un d ary sca n . 6. 4 .2 disabling the scan feature it is possi b le to op e rate t h e gdd r 3 witho u t us i ng the b o un d a r y sc a n f e ature. sen ( a t u - 4 o f 1 3 6 - ball packag e ) s h ou l d be tied lo w (vss) to p r e vent t h e d e vice fr o m entering t h e b o und a ry sc a n mod e . the o t h e r pins w h ich a r e used for scan m o de, res, mf, w dqs0 a n d cs w i ll be o p erating a t normal gddr3 f unctio n al i t i e s w h en sen is d easserted. www.datasheet.co.kr datasheet pdf - http://www..net/
W641GG2JB 1 - gbit gddr 3 graphics sdram publication release date: apr, 22 , 20 11 - 29 - revision a01 - 002 6. 4 .2.1 internal block diagram (reference only) 6. 4 .2.2 boundary scan exit o r der bit# ball bit# b all bit# ball b it# ball b it# ball bit# b a l l 1 d - 3 13 e - 10 25 k - 1 1 37 r - 10 4 9 l - 3 6 1 g - 4 2 c - 2 14 f - 10 26 k - 1 0 38 t - 11 5 0 m - 2 62 f - 4 3 c - 3 15 e - 11 27 k - 9 3 9 t - 10 5 1 m - 4 63 f - 2 4 b - 2 16 g - 10 28 m - 9 4 0 t - 3 5 2 k - 4 6 4 g - 3 5 b - 3 17 f - 11 29 m - 1 1 41 t - 2 5 3 k - 3 65 e - 2 6 a - 4 18 g - 9 3 0 l - 10 4 2 r - 3 54 k - 2 6 6 f - 3 7 b - 10 1 9 h - 9 31 n - 11 43 r - 2 5 5 l - 4 67 e - 3 8 b - 11 2 0 h - 1 0 3 2 m - 10 4 4 p - 3 56 j - 3 9 c - 10 2 1 h - 1 1 3 3 n - 10 4 5 p - 2 57 j - 2 10 c - 11 22 j - 11 34 p - 1 1 46 n - 3 5 8 h - 2 11 d - 10 23 j - 10 35 p - 1 0 47 m - 3 5 9 h - 3 12 d - 11 24 l - 9 3 6 r - 11 4 8 n - 2 6 0 h - 4 p i n s u n d e r t e s t t i e t o l o g i c 0 d m 0 d q 5 d q 4 d e d i c a t e d s c a n d f f p e r s i g n a l u n d e r t e s t t h e f o l l o w i n g l i s t s t h e r e s t o f t h e s i g n a l s o n t h e s c a n c h a i n : d q [ 3 : 0 ] , d q [ 3 1 : 6 ] , r d q s [ 3 : 1 ] , d m [ 3 : 1 ] , c a s # , w e # , c k e , b a [ 2 : 0 ] , a [ 1 1 : 0 ] , c k , c k # a n d z q t w o r f u s ( j - 2 a n d j - 3 o n 1 3 6 - b a l l p a c k a g e ) w i l l b e o n t h e s c a n c h a i n a n d w i l l r e a d a s a l o g i c D 0 t h e f o l l o w i n g l i s t s t h e s i g n a l s n o t o n t h e s c a n c h a i n : v d d , v s s , v d d q , v s s q , v d d a , v s s a a n d v r e f r d q s 0 r e s ( s s h , s c a n s h i f t ) c s # ( s c k , s c a n c l o c k ) w d q s 0 ( s o u t , s c a n o u t ) s e n , s c n e n a b l e m f ( s o e # , o u t p u t e n a b l e ) p u t s d e v i c e i n t o s c a n m o d e a n d r e - m a p s p i n s t o s c a n f u n c t i o n a l i t y d d d d c k d q c k d q d q d q c k c k www.datasheet.co.kr datasheet pdf - http://www..net/
W641GG2JB 1 - gbit gddr 3 graphics sdram publication release date: apr, 22 , 20 11 - 30 - revision a01 - 002 notes : 1. wh e n t h e device is in scan mod e , the mirror fu n ct i on will b e disa b led a n d none o f the pi n s are rema p pe d . 2. since the other i n put of t h e mux for dm0 tied to gnd, the d e vice wi l l o u tp u t the c ontin u ous zeros a f ter scan n ing a bit # 6 7, if the chip s tays in scan shift mode. 3. an unco n nected cs1 # a n d a 1 2 on the bo a rd w ill be re a d as u nd e fi n ed. 6. 4 .2.3 scan pin description p a ckage ball symbol normal fun c tion type description v - 9 ssh res input scan shift: c apture t h e d a ta i nput from the p a d a t lo g ic low and sh i f t the data on the ch a in at l ogic high. f - 9 sck cs inp u t scan clock: not a true c l ock, cou l d be a sing l e pulse o r seri e s o f pu l ses. all scan i n puts w i ll be refere n ced to ris i ng ed g e of the scan clock d - 2 so u t w dqs0 output scan o u tp u t v - 4 sen s en i np u t scan enabl e : l ogic high e n abl e s the d e vice into scan mode a n d will be dis a bled a t l o gic lo w . must b e ti e d to gnd when n o t i n u se. a - 9 s oe mf inp u t scan o u tp u t enable: ena b les (r e g istered low) a n d d isab l es (r e g istered high) so u t data. th i s p i n will be ti e d to v d d or gnd throu g h a r e sist o r (typically 1 k notes : 1. wh e n sen i s asserte d , no comman d s a r e to be ex e cut e d by the gddr 3 . t h is app l ies both to u ser c o mma n ds and manufacturi n g c o mm a nds which may exist w h ile res is de a ss e rt e d. 2. t h e scan functi o n can b e used right after bri n ging up v dd / v d dq o f the device. no initi a liza t ion sequ e nce o f the d e vice i s req u ired. after leav i ng t h e sc a n fu n ct i on it i s re q u ired to run t h rou g h the com p lete initi a lizati o n s e qu e nce. 3. in scan mo d e all termin a ti o n s for cmd/add and dq, dm, r d qs and w dqs are switched o f f. 4. in a do u ble - l oad clam - she l l co n f i gurati o n, sen w i ll b e a ssert e d to both d e vices. se p a rate two so e s sho u ld be p rovid e d to t o p a nd bottom d e vices to access the scan n ed outp u t. w hen e i t h er of the d e vices i s in scan mod e , soe f o r t h e o t h e r d e vice which i s n o t in a scan w i ll be dis a ble d . 6. 4 .2.4 scan dc electrical characteristics and ope r ating condition p a rameter/condition sy m b ol min. ma x . units note in p u t h igh (lo g ic 1) v o lt a g e v ih (dc) v r e f +0 . 1 5 1,2 in p u t l o w (log i c 0 ) vo l t a g e - v il (dc) v ref - 0.15 v 1 , 2 notes : 1. the p arameter applies only w hen sen is asserted. 2. all voltag e s r eferenced to gn d . www.datasheet.co.kr datasheet pdf - http://www..net/
W641GG2JB 1 - gbit gddr 3 graphics sdram publication release date: apr, 22 , 20 11 - 31 - revision a01 - 002 6. 4 .2.5 scan capture timing 6. 4 .2.6 scan shift timing s c k s e n s s h s o e # p i n s u n d e r t e s t v a l i d t s e s t s c s t s d s t s d h l o w d o n t c a r e s c k s e n s s h s o e # s o u t t s a c t s o h t s c s t s c s t s e s s c a n o u t b i t 0 s c a n o u t b i t 1 s c a n o u t b i t 2 s c a n o u t b i t 3 d o n t c a r e www.datasheet.co.kr datasheet pdf - http://www..net/
W641GG2JB 1 - gbit gddr 3 graphics sdram publication release date: apr, 22 , 20 11 - 32 - revision a01 - 002 6. 4 .2.7 scan ac electrical characteristic p a ram e ter/condition symbol min. max. units note clock clock c y cle time t s c k 40 n s 1 s c an comm a nd ti m e sc a n ena b le setup time t ses 20 n s 1 , 2 sc a n ena b l e ho l d t i me t seh 20 n s 2 s can c o m m and setup time for ssh, soe a n d sout t s c s 14 n s 1 sc a n c o mm a nd ho l d time for ss h , soe a n d sout t s c h 14 n s 1 s c a n c a pt u re time sc a n c a pture setup t i me t s d s 10 n s 1 sc a n c a pture ho l d time t s d h 10 n s 1 s c an shift time sc a n c l ock to val i d sc a n output t sac 10 n s 1 sc a n c l ock to scan o u t p ut h o ld t soh 1 . 5 n s 1 notes: 1. the p arameter applies only w hen sen is asserted. 2. scan e n able should be issued earlier than other sc a n commands by 6 ns. 6. 4 .3 s can initialization the initia l ization seq u ence f o r t h e b ou n dary scan function a li t y d e pe n ds on the inten d ed sgr a m o p eration mod e . th e re are tw o mod e s t o d i sti n guis h . th e firs t m o d e is the sta n d - alo n e mo d e . in the sta n d - alo n e mo d e the sgram i s sup p osed to s u pp o rt t h e bou n dary sc a n f u nct i on a lity o n ly, the u ser d oes n o t inte n d to o perate the dram in its o rdin a ry functi o nal i t y aft e r or pr i o r to t h e e n tering of the bo u ndary scan fu n ct i ona l ity. t h e p u rpose of the st a nd - al o ne mode cou l d b e a co n nectivity test at the man u f a ctur i ng site. the s e c o nd mode i s the re g u l a r sgram functi o nal i t y. with t h is comm o n mode the b o un d ary scan fu n cti o na l ity can b e ena b led after the sgram h a s be e n i n it i a l i z e d by the reg u lar p o wer - up and sgram initia l ization s e qu e nce. w h en the bou n dary scan fu n ct i ona l ity is left the re g u l a r sgram i n i ti a l i z a t i on seq u ence h a s to be re - iterated. 6. 4 . 3.1 s can initialization for stand - alone mode the sgram ne e ds to fo l low the g iven se q ue n ce to s u pport the b o und a ry scan f u nct i ona l ity i n t h e stand - al o ne mo d e . there is n o ext e rnal clock for the w h ole se q uence n eed e d. s e qu e nc e f l ow: 1. ext e r n al volta g es (vdd/vddq/v r ef) need to be stab l e for 20 0 s, sen has to be kept low. 2. bring sen up to h igh state to e n t e r b oun d ary scan fu n cti o na l ity. 3. o p erate bo u ndary scan f u nction a lity a cc o r d ing to the scan f e atures given i n chapter . 4. bou n dary sc a n c a n be exited by bri n gi n g sen l o w o r simp l y b y switch i ng pow e r o f f. the scan i n itia l ization se q uence for t h e sta n d - alo n e m o de is shown in fi g ure . www.datasheet.co.kr datasheet pdf - http://www..net/
W641GG2JB 1 - gbit gddr 3 graphics sdram publication release date: apr, 22 , 20 11 - 33 - revision a01 - 002 6.4.3.2 scan initialization for stand - alone mode 6. 4 . 4 s can initialization in regular sgram operation the initi a lizati o n s e qu e nce of the b o un d ary scan functi o nal i t y in reg u lar s g ram op e r a t i on has to f o llow the g i v e n sequ e nce. s e qu e nc e f l ow: 1. ext e r n al volta g es ( v dd / v d d q / v r e f ) n e ed to b e sta b le for 2 0 0 s, res has to b e kept l o w, e xt e r n al clock has to b e sta b le prior to res g oes high 2. bring res high and keep cl o ck stable for 700tcks, cke will be latched by r i sing res edge, keep t ath / t a ts 3. bring sen up to h igh state to e n t e r b oun d ary scan fu n cti o na l ity 4. o p erate bo u ndary scan f u nction a lity a cc o r d in g ly to the scan features giv e n i n ch a pte r . 5. bou n dary sc a n c a n be exited by bri n gi n g sen l o w 6 . wa i t t sn for brin g ing up res, prior to b ring i ng res to h i gh st a t e extern a l has to b e sta b le 7. after res i s a t hi g h state wa i t 7 0 0tck 8. co n t i n ue with reg u lar i n itial i z a t i on seq u ence (pre - all, emrs, m r s) v d d v d d q v r e f c l k / c l k # s s h [ r e s ] s e n s c k [ c s # ] s o e [ m f ] s o u t [ w d q s ] p i n s u n d e r t e s t v a l i d t s d s t s d h t s c s t s e s t s c s t s c h v a l i d t s d s t s d h t s c s t s c h t s c s s c a n o u t b i t 0 b o u n d a r y s c a n m o d e t = 2 0 0 u s p o w e r - u p : v d d / v d d q / v r e f s t a b l e d o n t c a r e www.datasheet.co.kr datasheet pdf - http://www..net/
W641GG2JB 1 - gbit gddr 3 graphics sdram publication release date: apr, 22 , 20 11 - 34 - revision a01 - 002 the steps 1 and 2 are necess a ry to e nab l e the termin a t i on f o r t he command/a d dress p ins. they are part o f the r e gu l ar sgram in i t i a liz a t i on. they are req u ired if the u ser w a nts to issue comman d s b e tw e en to e n tering o f t h e bou n dary sc a n f u nct i on a lity and the p o wer - up s e qu e nce. the entering of the b ou n dary scan mode is r e setti n g the comman d / a ddress terminati o n valu e s and all emrs/mrs sett i ngs. t h erefore th e y have to be i n itia l ized a ga i n after the b oun d ary scan fu n cti o nary h a s be e n l e ft. f i g u r e (boundary scan exit sequence) sh o ws the scan i n itial i zation seq u ence for regu l ar sgram o perati o n. 6. 4 .4.1 scan initialization sequence within regular sgram mode v d d v d d q v r e f c l k / c l k # s s h [ r e s ] s e n s c k [ c s # ] s o e [ m f ] s o u t [ w d q s ] p i n s u n d e r t e s t c k e s c a n o u t b i t 0 v a l i d v a l i d b o u n d a r y s c a n m o d e r e s e t a t p o w e r - u p t = 2 0 0 u s d o n t c a r e t s c s t s c s t s c h t s c s t s c h t s c s t s e s t s d s t s d h t s d s t s d h t s d h t s d s t a t s t a t h 7 0 0 t c k p o w e r - u p : v d d s t a b l e v a l i d www.datasheet.co.kr datasheet pdf - http://www..net/
W641GG2JB 1 - gbit gddr 3 graphics sdram publication release date: apr, 22 , 20 11 - 35 - revision a01 - 002 6. 4 . 5 s can exit sequence f i g u r e sho w s t h e scan ex i t s e qu e nce. t h is fi g u re s h ow the exiti n g o f the b o un d ary scan f u nct i on a lity in con j ugati o n w i th the a pp e nded r e gul a r sgram i n itial i zat i on seq u ence to bring the sgram a g ain in a w e ll defi n ed st a t e . 6. 4 .5.1 boundary scan exit sequence 6. 4 .5.2 scan ac electrical parameter p a rameter symb o l lim i t val u es u n it note min max. t resl t r e sl 20 - ns t sn t sn 20 - ns c k e s e n r e s c l k / c l k # s o u t 7 0 0 t c k t a t s t a t h t r e s l t s n i n v a l i d s t a b l e c l o c k s t a n d a r d p o w e r u p s e q u e n c e s t a r t i n g w i t h p r e a l l www.datasheet.co.kr datasheet pdf - http://www..net/
W641GG2JB 1 - gbit gddr 3 graphics sdram publication release date: apr, 22 , 20 11 - 36 - revision a01 - 002 6. 5 p rogrammable impedance output drivers and active terminations 6. 5 .1 gddr3 io driver and termination the gddr3 graphics sdram is e q ui p ped with prog r amma b le imped a nce output b u ff e r s and active t e rm i natio n s . t h i s al l o ws the user to match the driver i m pedance to the system i m pedance. to a d just the im p eda n ce of dq[ 0 : 3 1] a n d r dqs [ 0 :3] , an ext e rn a l p recision r e sist o r (zq) is c o nnected b e t w een the zq pin and vss. the va l ue of the r e sist o r must be six tim e s t h e v a lue of the d e s i red imped a nce. for e xample, a 2 40 resistor is r e qu i r e d for an output i m p ed a nce o f 40 . t h e ra n ge of zq i s 210 t o 27 0 , g i ving an outp u t imped a nce r a nge of 3 5 to 4 5 ( o ne sixth the v a lue of zq w i t h in 10 % ). the val u e of zq i s used to cali b rate the i n ternal dq t e rmi n ation resistors of dq[0:31] , w d qs [ 0 : 3 ] a n d dm [ 0 : 3] . t h e two termi n a tion va l ues t h at are se l e ctable u s i ng emrs[ 3 : 2 ] are zq / 4 and zq / 2 . the v a lue o f zq is a lso used to c a libr a te the i n ternal add re s s comma n d t e rm i nation r e sist o rs. the i n puts termi n a ted in th i s m a nner a re a[ 0 : 1 1 ], a[ 1 2 ],cke#, cs 0# , cs 1# , ras#, c a s#, w e# . the two termin a t i on va l ues that are s e lectab l e u p on p o r up ( c ke l a tch e d low to high transition of res) are zq / 4 and zq / 2.. res, mf , clk and clk# are not internally terminated. if n o res i sta n ce is con n ect e d to zq, an intern a l d e fault v a lue of 2 4 0 will be us e d . in this case, no cal i bration wi l l b e p e rf o rm e d. www.datasheet.co.kr datasheet pdf - http://www..net/
W641GG2JB 1 - gbit gddr 3 graphics sdram publication release date: apr, 22 , 20 11 - 37 - revision a01 - 002 6. 5 .1.1 output deiver simplified schematic 6. 5 .1.2 ra n ge of external resistance zq p a rameter symbol min. nom. m ax. units note extern a l resistance val u e z q 210 240 270 6. 5 .1.3 termination types and activation b a ll t e rm i n a t i on t y pe t e rmi n a t ion ac ti va tion clk, c l k # , rdqs[0:3] , z q , r e s, mf no termin a t i on cke, cs0 # , cs 1 # , ra s # , c a s # , w e #, b a0 - ba2 , a [ 0 : 11 ] , a [12] add / cmds always o n dm [ 0 : 3 ] , w d qs[ 0 : 3 ] dq a lway s on dq[ 0 :31] dq cmd bus snoo p ing r e a d t o o t h e r r a n k o u t p u t d a t a r e a d t o o t h e r e n a b l e d q v d d q v s s q www.datasheet.co.kr datasheet pdf - http://www..net/
W641GG2JB 1 - gbit gddr 3 graphics sdram publication release date: apr, 22 , 20 11 - 38 - revision a01 - 002 6. 5 . 2 s elf calibration for driver and termination the o u t p ut imp e da n ce is up d ated duri n g all aref commands. th e se u pdates are used to c o m p ensate f o r vari a t i ons in supp l y v o ltage a n d temp e rature. impe d an c e up d ates d o not a f fect d e vice op e rat i on. no act i vity on the address, c o mm a nd and d a ta bus is a ll o wed dur i ng a minimum keep out time t ko aft e r the autorefresh command h a s b een issu e d . 6. 5 .2.1 termination update keep out time after autorefresh command to gua r a ntee optimum d r iver impedance after power - up, the gddr3 graphics sdram needs 700 cycles after the c l ock is applied and sta b le to cal i brate the im p eda n ce up o n p o wer - up. t h e user c a n op e rate t h e pa r t with few e r th a n 7 0 0 cycles, but optimal output impe d ance wi l l n o t b e guar a n teed. the gddr3 grap h ics ram proce e ds i n t h e fo l low i ng mann e r for self cali b ration: th e pm o s d e vice is c a li b r a t e d a ga inst th e e xt e r n al zq r e sistor v a lu e . first one pmos l eg i s cali b rated a ga i nst zq. the number o f legs u sed for the t e r m i n ators (dq and a d d/ c m d ) and the p m os dr i v e r is re p r e sented in t a b l e . n e xt, o n e nmos leg is cal i brated ag a inst the a l r ea d y ca l ibrated pmos le g . the nmos driver uses 6 nmos le g s. a d d . d q c o m . c l k # c l k a r f t k o n o p d o n t c a r e k e e p o u t t i m e a r f : a u t o r e f r e s h www.datasheet.co.kr datasheet pdf - http://www..net/
W641GG2JB 1 - gbit gddr 3 graphics sdram publication release date: apr, 22 , 20 11 - 39 - revision a01 - 002 6. 5 .2.2 n u mbe r o f l eg s u se d f o r te r m in a t or a n d dr i ve r s e l f c a l i br a t i o n note : 1. emrs[3:2] = 00 disables the a d d and cmd terminations a s w e ll. f i g u r e re p resents a s i m p lified sc h ematic o f the cal i bration circu i ts. first, the str e ngth c ontrol b i ts are a d justed in such a w a y th a t the vddq v o lt a ge i s divi d ed e q ual l y betwe e n the pmos d evice a n d the zq r e s i st o r . the b e st b it p a tt e r n will cause the c o mparator to switch t h e pmos match s i gnal o u t p ut va l ue. in a second step, the nfet is c a libr a ted a gai n st t h e a lrea d y c a li b r a t e d pfet. in the s a me mann e r, the best co n t r o l b i t c o m b inati o n w i ll ca u se the c o m p arator to sw i t ch t h e nmos m a tch s i gn a l o u tput v a lu e . 6. 5 .2.3 self calibration of pmos and nmos legs cke (at res) t e rmin a t i on num be r of l e gs n o te te rminator add / c m d 0 z q /2 2 1 zq 1 e m rs[3 : 2 ] d q 00 d i sabl e d 0 1 10 z q /4 4 11 z q /2 2 driver pmos zq/6 6 n m os z q /6 6 v d d q v d d q / 2 v d d q / 2 v d d q v s s q s t r e n g t h c o n t r o l [ 2 : 0 ] p m o s c a l i b r a t i o n v s s q s t r e n g t h c o n t r o l [ 2 : 0 ] n m o s c a l i b r a t i o n v s s q m a t c h z q www.datasheet.co.kr datasheet pdf - http://www..net/
W641GG2JB 1 - gbit gddr 3 graphics sdram publication release date: apr, 22 , 20 11 - 40 - revision a01 - 002 6. 5 . 3 d ynamic switching of dq terminations the gddr3 grap h ics r am wi l l disa b le its da t a t e rm i nators when a r e ad o r dterd i s c o mma n d is detected. the termi n a tors are disa b led starting a t cl - 1 cl o cks after the read / dte r dis command i s d e tect e d and the d u ration i s 4 cl o cks. in a two r a nk syst e m, b o th d e vices wi l l sn o op the bus for a read / dterdis command to either de v ice and both w ill d isa b le the i r termi n a tors i f a read / dte r dis command is d e t e cte d . t h e ad d r e ss a n d comm a nd term i nators are alw a ys e n ab l ed. 6. 5 .3.1 odt disable timing during a read command a d d . d q c o m . c l k # c l k r d q s d q t e r m i n a t i o n r d n / d n / d n / d n / d n / d n / d n / d n / d n / d b / c d 0 d 1 d 2 d 3 0 1 2 3 4 5 6 7 8 9 c a s i a t e n c y = 5 d o n t c a r e c o m . : c o m m a n d d x : d a t a f r o m b / c a d d r . : a d d r e s s b / c b / c : b a n k / c o l u m n a d d r e s s r d : r e a d n / d : n o p o r d e s e l e c t d a t a t e r m i n a t i o n s a r e d i s a b l e d www.datasheet.co.kr datasheet pdf - http://www..net/
W641GG2JB 1 - gbit gddr 3 graphics sdram publication release date: apr, 22 , 20 11 - 41 - revision a01 - 002 6. 5 .4 output impedance and ter m ination dc electrical characteristics the driver and termi n a tion i m p ed a nces are d e t e rm i ned b y a pp l y i ng v d d q /2 nomin a l at t h e corresp o ndi n g in p u t/ o u t p ut and b y m e asuri n g the curr e nt flow i ng into or out of the d e vice. v d d q i s set to the n o m i nal va l ue. i o h is t h e current fl o wing o u t of dq w h en t h e pull - up t r ans i s tor is activated and the dq termi n a tion d i sabl e d . i o l is t h e c u rr e n t flo w ing i n to dq when the pu l l - down transistor is act i vated and t he dq termi n a t i on d i s a bl e d . i t c ah(z q ) i s the current f l owi n g out o f the t e rm i nation o f comman d s a nd addresses for a zq termin a ti o n valu e . 6. 5 .4.1 dc electrical characteristic p a rameter z q v a l ue l imit values un i t n o te 240 mi n . max. i oh zq/6 20.5 25.0 ma 1,2 i ol zq/6 20.5 25.0 ma 1 ,2 i t c ah(z q) zq 3.4 4 .2 ma 1,2 notes : 1. measurement p erfo r med with v d dq (nominal) and by applying v d d q/2 at the cor r espo n ding i nput / output. 0 c tc 10 5 c 2. for 1.8 v v dd / v d dq power supply www.datasheet.co.kr datasheet pdf - http://www..net/
W641GG2JB 1 - gbit gddr 3 graphics sdram publication release date: apr, 22 , 20 11 - 42 - revision a01 - 002 6. 6 m ode register set command (mrs) the mode register stores the data for controlling the operation modes of the memory. it programs cas latency, test mode, dll reset, the value of the write latency and the burst length. the mode register must be written after power up to operate the sgram. during a mode register set command the address inputs are sampled and stored in the mode register. the mode register content can only be set or changed when the chip is in idle state. for non - read commands following a mode register set a delay of tmrd must be met. to apply an mrs command, cs0 has to be used. 6. 6 .1 mode register set command 6. 6 . 2 mode registers three mode registers mrs, emrs1 and emrs2 define the specific mode of op eration. all mode registers are initialized upon power - up as indicated below. all functions controlled by mode register emrs3 and some high - speed op tions in the other registers as outlined below shall be deactivated or deleted such that programming of the respective register bits has no effect. 6. 6 . 2.1 mode register (mrs) the mode register controls operating modes such as burst length, burst type, cas latency, write latency, dll reset and test mode as shown in figure . the register is programmed vi a the mode register set command with ba0=0, ba1=0 and ba2=0. = d o n ' t c a r e ( h i g h ) c l k c k e c s # r a s # c a s # w e # a 0 - a 1 1 b a 0 c o d 0 b a 1 , b a 2 0 c l k # c o d : c o d e t o b e l o a d e d i n t o t h e r e g i s t e r . www.datasheet.co.kr datasheet pdf - http://www..net/
W641GG2JB 1 - gbit gddr 3 graphics sdram publication release date: apr, 22 , 20 11 - 43 - revision a01 - 002 6. 6 .2.2 mode re gister (mrs) 6. 6 .2.3 mode register set timing b a 2 b a 1 b a 0 a 1 1 a 1 0 a 9 a 8 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 b t d l l t m 0 0 0 w l c a s l a t e n c y b l b l a 2 a 1 a 0 4 * 0 1 0 8 0 1 1 r f u a l l o t h e r s m o d e a 7 n o r m a l * 0 t e s t m o d e 1 t e s t m o d e b u r s t l e n g t h w l a 1 a 1 0 a 9 3 * 0 1 1 4 1 0 0 5 1 0 1 6 1 1 0 7 1 1 1 w r i t e l a t e n c y b t a 3 s e q u e n t i a l * 0 r f u 1 b u r s t t y p e l a t e n c y a 6 a 5 a 4 8 * 0 0 0 9 0 0 1 1 0 0 1 0 1 1 0 1 1 1 2 1 0 0 c a s l a t e n c y d l l r e s e t a 8 n o * 0 y e s 1 1 3 1 0 1 1 4 1 1 0 7 1 1 1 n o t e : t h e d l l r e s e t b i t i s s e l f - c l e a r i n g * d e f a u l t v a l u e a t p o w e r - u p d l l r e s e t p a n o p m r s n o p n o p a . c . n o p r d t r p t m r d t m r d r m r s : m r s c o m m a n d p a : p r e a l l c o m m a n d a . c . : a n y o t h e r c o m m a n d a s r e a d d o n ' t c a r e r d : r e a d c o m m a n d c o m m a n d c l k c l k # www.datasheet.co.kr datasheet pdf - http://www..net/
W641GG2JB 1 - gbit gddr 3 graphics sdram publication release date: apr, 22 , 20 11 - 44 - revision a01 - 002 6 . 6 .3 burst length and burst type 6. 6 . 3. 1 burst length read and write accesses to the gddr3 graphics sdram are burst - oriented, with a burst le ngth of 4 or 8 as programmed in bits a0 - a2. when a read or write command is issued, a block of columns equal to the burst length is effectively selected. all accesses for that burst take place within this block, meaning t hat the burst will wrap within the block if a boundaryis reached. the block is uniquely selected by address bits a2 - a7,a9. the access order within a burst is fixed, and address bits a0 and a1 are ignored as shown in table . the only supported burst type is sequential. 6. 6 .3.2 b urst type acc e ss e s w i th i n a given b a nk m u st be pro g ramm e d to be se q ue n ti a l. t h is is done u sing the mode re g ister s e t command (a3). th i s d e vice do e s n o t sup p ort the b u rst interl e a ve m o de. 6. 6 .3.2.1 b u rs t d e f i n i t i on burst length column address order of accesses within a burst a2 a1 a0 4 x x 0 - 1 - 2 - 3 8 0 x x 0 - 1 - 2 - 3 - 4 - 5 - 6 - 7 1 x x 4 - 5 - 6 - 7 - 0 - 1 - 2 - 3 the va l ue a p pli e d at the b a lls a0 a nd a1 f o r the co l u mn addr e s s is Ddon t care. 6. 6 .4 cas latency the read latency, or cas latency, is the delay between the registration of a read command and the avai lability of the first piece of output data. the l atency is set using bits a4 - a6. if a read command is registered at clock edge n, and the latency is m clocks, the d ata will be av ailable nominally coincident with clock edge n + m. the high - speed option for cas latencies of 13 to 20 shall be deleted or deactivated. 6. 6 .5 w rite latency the write latency (wl) is the delay, in clock cycles, between the registration of a write command and the availability of the first bit of input data. the latency is set using bits a9 - a11. if a write command is registered at clock edge n, and the latency is m clocks, the data will be available nominally coinciden t with clock edge n + m. www.datasheet.co.kr datasheet pdf - http://www..net/
W641GG2JB 1 - gbit gddr 3 graphics sdram publication release date: apr, 22 , 20 11 - 45 - revision a01 - 002 6. 6 . 6 dll reset the normal operating mode is selected by issuing a mode register set comma nd with bit a8 set to zero, and bits a0 - a7 and a9 - a11 set to the desired values. a dll reset is initiated by issuing a mode register set command with bit a8 set to one, and bits a0 - a7 and a9 - a12 set to the desired values. the regis ter bit is self clearing meaning that it returns back to the value ?0 after the dll reset function has been issued. 6.6.7 t est mode the normal operating mode is selected by issuing a mode register set command with bit a7 set to ?0, and bitsa0 - a6 and a8 - a11 set to the desired values. programming bit a7 to ?1 places the device into a test mode that isonly to be used by the dra m manufacturer. no functional operation is specified with test mode enabl ed. 6. 7 e xtended mode register set command (emrs1) the extended mode register is used to control multiple operation modes of the device. the most important one is the organization as a 1 - cs or a 2 - cs device. furthermore, it is used to set the output driver impedance value, the termination impedance value, the write recovery time value for write with autoprecharge. it is used as well to enable/disable the dll, to issue the vendor id. there is no default value for the extended mode register. therefore it must be written after power up to operate the gddr3 gra phics ram. the extended mode register can be programmed by performing a normal mode register set operation and setting the ba0 bit to high. all other bits of the emr register are reserved and should be set to low. the extended mode register must be loaded when all banks are idle and no burst are in progress. the controller must wait the specified time t mrd before initiating any subsequent operation (figure : extended mode register 1) . the timing of the emrs command operation is equivalent to the timing of the mrs command operation.to apply an emrs command, cs0 has to be used. www.datasheet.co.kr datasheet pdf - http://www..net/
W641GG2JB 1 - gbit gddr 3 graphics sdram publication release date: apr, 22 , 20 11 - 46 - revision a01 - 002 6. 7 .1 extended mode register set command 6. 7 .2 extended mode register 1 (emrs1) the extended mode register 1 controls operating modes such as output driver impedance, da ta termination, address/command termination, dll on/off, write recovery and vendor id as shown in figure . it also selects between 1 - cs mode and 2 - cs mode configuration. the register is progr ammed via the mode register set command with b a0=1, ba1=0 and ba2 set to the desired configuration. = d o n ' t c a r e ( h i g h ) c l k c k e c s # r a s # c a s # w e # a 0 - a 1 1 b a 0 c o d 1 b a 1 0 c l k # c o d : c o d e t o b e l o a d e d i n t o t h e r e g i s t e r . b a 2 m o d e www.datasheet.co.kr datasheet pdf - http://www..net/
W641GG2JB 1 - gbit gddr 3 graphics sdram publication release date: apr, 22 , 20 11 - 47 - revision a01 - 002 6. 7 .2.1 extended mode register 1 (emrs1) notes : 1. default termination values at power up. 2. the odt disable function disables all terminators on th device. 3. if the user activates bits in the extended mode register in an optional field, either the optional field is activated (if option implemented in the device) or no action is taken by the device (if option not implemented). 4. wr (write recovery time for auto precha rge) in clock cycles is calculated by dividing twr (in ns) and rounding up to the next integer (wr[cycles] = twr[ns] / tck[ns]). the mode register must be programmed to this value. b a 2 b a 1 b a 0 a 1 1 a 1 0 a 9 a 8 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 m o d e 0 1 r f u v e n d o r i d a d d / c m d t e r n i n a t i o n w r d l l w r i t e r e c o v e r y d a t a t e r m i n a t i o n o c d i m p e d a n c e b a 2 c h i p s e l e c t m o d e a 1 0 v e n d o r i d a 6 d l l a 1 a 0 o c d i m p e d a n c e d a t a t e r m i n a t i o n a 2 a 3 w r i t e r e c o v e r y a 4 a 5 a 7 a d d / c m d t e r n i n a t i o n a 8 a 9 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 4 5 6 7 8 9 1 0 ( * ) a u t o c a l ( * ) 3 5 o h m s 4 0 o h m s 4 5 o h m s d i s a b l e d r f u z q / 4 z q / 2 ( * ) o n ( * ) o f f o n o f f ( * ) 1 - c s 2 - c s z q / 4 z q / 2 z q / 2 ( * ) z q ( * ) = d e f a u l t v a l u e a t p o w e r - u p www.datasheet.co.kr datasheet pdf - http://www..net/
W641GG2JB 1 - gbit gddr 3 graphics sdram publication release date: apr, 22 , 20 11 - 48 - revision a01 - 002 6. 7 .2.2 extended mode register set timing 6. 7 .3 chip select mode mode emrs1[ba2] emrs2[a5] pin for cs1# pin for a12 1 - cs mode, non - merged 0 0 na j - 2 2 - cs mode 0 1 j - 3 na 1 0 1 - cs mode, merged 1 1 na j - 3 6. 7 . 4 dll the dll is enabled by default. if dll - off operation is desired, the dll must be disabled by setting bit a6 to '1'. once enabled, the dll requires 1000 cycles to lock. 6. 7 . 5 w rite recovery the programmed wr value is used for the auto precharge feature along with trp to determine tdal. wr must be programmed with a value greater than or equal to [ru{twr/tck}], where ru stands for round up, twr is the analog value and tck is the operating clock cycle time. the high - speed option for write recovery values of 11 to 20 shall be deleted or deactivated. 6 . 7 . 6 t ermination rtt the data termi n a t i on, rtt, is u sed to s e t the value of t h e i n t e r n al termi n a t i on r e s i st o r s. the gddr3 dram sup p orts zq / 4 and zq / 2 termin a t i on v a lu e s . the termin a ti o n may also be dis a bled for testing a n d o t h e r p u rposes. d a ta - , a d dress - and c o mm a nd - termin a ti o n are disa b led i n p a rall e l. the t e rmi n a t ion rtt are c o ntroll e d in d ep e nde n t l y from the outp u t dr i v e r imp e dance va l ues. p a n o p e m r s n o p n o p a . c . t r p t m r d e m r s : e x t e n d e d m r s c o m m a n d p a : p r e a l l c o m m a n d a . c . : a n y c o m m a n d d o n ' t c a r e c o m m a n d c l k c l k # www.datasheet.co.kr datasheet pdf - http://www..net/
W641GG2JB 1 - gbit gddr 3 graphics sdram publication release date: apr, 22 , 20 11 - 49 - revision a01 - 002 6. 7 . 7 impedance autocalibration of output buffer and active terminator gddr3 graphics sdram s offer autocalibrating impedance output buffers and on - die ter minations (odt). this enables a user to match the driver impedance and terminations to the system within a given range. to adjust the impedance, an external precision resistor shall be connected between the zq pin and vssq. a nominal resistor value of 240 is equivalent to 40 pulldown, 40 pullup and 60 odt nominal impedances. if no resistance is connected to the zq pin, a default value of 240 is assumed and no calibration is performed. the output driver and on - die termination impedances are updated during all refresh commands to compensate for variations in supply voltage and temperature. the impedance updates are transparent to the system. table provides an overview of the odt settings controlled by emrs 1. 6. 7 . 7 .1 impedance options signal odt activation emrs1 control bits clk,clk#,res,mf,sen no odt - cke,cs0#,cs1#,ras#,cas#,we#,ba0 - ba2,a0 - a12 always on a8 - a9 dm0 - dm3,wdqs0 - wdqs3 always on a2 - a3 dq0 - dq31 always on except for reads (bus snooping) a2 - a3 rdqs0 - rdqs3 no odt - 6. 7 .7 .2 timing of vendor code and revision id generation on dq[7:0] e m r s n / d n / d n / d n / d n / d n / d n / d n / d a d d 0 1 2 3 4 5 6 7 8 9 1 0 a [ 9 : 0 ] , a 1 1 d q [ 7 : 0 ] c o m . c l k # c l k r d q s a 1 0 v e n d e r c o d e a n d r e v i s i o n i d t r i d o n t r i d o f f e m r s n / d a d d d o n t c a r e a d d : a d d r e s s e m r s : e x t e n d e d m o d e r e g i s t e r s e t c o m m a n d n / d : n o p o r d e s e l e c t www.datasheet.co.kr datasheet pdf - http://www..net/
W641GG2JB 1 - gbit gddr 3 graphics sdram publication release date: apr, 22 , 20 11 - 50 - revision a01 - 002 6. 7 . 8 output driver impedance bits a0 and a1 define the driver strength. the auto calibration setting enables the auto - calibration functionality for the pulldown, pullup and termination over process, temperature and voltage changes. the 35 , 40 and 4 5 options enable factory settings for the pulldown, pullup driver strength and termination. with any of those options enabled, driver strength and termination are expected to change with process, voltage and temperature. ac timings are only guaranteed with auto calibration. 6. 7 . 9 data termination bits a2 and a3 define the data termination value for the on - die terminati on (odt) for the dq pins in combination with the driver strength setting. the termination can be set to a value of zq/4 or zq/2; it may also be turned off. 6. 7 . 1 0 a ddress command termination bits a8 and a9 define the address/command termination. the termination can be set to a value of zq/4, zq/2 or zq. the setting overwrites the value defined upon power - up initialization. 6. 8 e xtended mode register 2 set command (emrs2) the extended mode register 2 is used to control ocd/odt impedance offsets. it can be programmed by performing a normal mode register set operation and setting the ba1 bit to high and ba0, ba2 bits to low. the extended mode register 2 must be loaded when al l banks are idle and no burst are in progress. the controller must wait the specified time t mrd before initiating any subsequent operation. the timing of the emrs2 command operation is equivalent to the timing of the mrs command operation. www.datasheet.co.kr datasheet pdf - http://www..net/
W641GG2JB 1 - gbit gddr 3 graphics sdram publication release date: apr, 22 , 20 11 - 51 - revision a01 - 002 6 . 8 .1 extended mode register 2 set command 6. 8 .2 extended mode register 2 (emrs2) the extended mode register 2 controls output driver and termination offs ets and merged mode as shown in figure . the register is programmed via the mode register set command with ba0=0, ba1=1 and ba2=0. the application mode function (mid range vs. high speed) on bit a0 and the temperature sensor self refresh function on bit a1 shall be deleted or deactivated. c k e c l k # c l k r a s # c s # c a s # w e # a 0 - a 1 1 b a 1 b a 0 , 2 0 1 c o d d o n t c a r e c o d : c o d e t o b e l o a d e d i n t o t h e r e g i s t e r www.datasheet.co.kr datasheet pdf - http://www..net/
W641GG2JB 1 - gbit gddr 3 graphics sdram publication release date: apr, 22 , 20 11 - 52 - revision a01 - 002 6. 8 .2.1 extended mode register 2 (emrs2) 6. 8 .2.2 impedance offsets the driver and termination impedances may be offset individually for output driver and data termination. the offset impedance step values correspond to a nominal value of tbd . with negative offset steps the drive strengths will be decreased and ron will be increased. with positive offset steps the drive strengths will be increased and ron will be decreased. 6. 8 .2.3 merged mode merged mode combines the specific pins of 1 - cs mode (a12) and 2 - cs mode ( cs1 # ) on a single physical pin (j - 3). 6. 8 . 3 ocd pull down offset the 1g gddr3 add the ab i lity to a dd an o f fset to the output im p eda n ce dr i ver set u s i ng t h e b it a[ 1 : 0 ] of the emrs. a r a nge from - 3 to +3 c a n be chos e n using a[11:9]. each steps corresp o nd to a n appr o x i mate c h ange o f 1 o h ms. the o f fset w ill be app l ied a l so o n autoc a l v a lue if se l e cted. the offs e t will be a p pl i ed also on autocal val u e if sel e cte d . w i th n e gative offset s t e ps the driver stren g th will be d e creased and t h e r o n wi l l be incre a s e d. with p o sitive o f fset st e p s the dr i v e r stre n g th wi l l be increas e d and r o n w ill be d e crease d . 6. 8 . 4 odt pull up offset the 1g gddr3 a dd the a b il i ty to a d d an off s et to the odt s e t u s i ng the b it a[3:2] of the emrs. a range from - 3 to +3 can be c h osen u sing a[8:6]. e a ch st e p s correspo n d to an a pproximate c h ange of 1 . 5 ohms. with n egative o f fset st e p s t h e t e rm i nation v a lue w i ll be i n cr e a sed. with pos i t i v e o f fset steps the t e rm i nation v a lue wi l l be decre a sed. b a 2 b a 1 b a 0 a 1 1 a 1 0 a 9 a 8 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 0 1 0 o c d p u l l d o w n o f f s e t o d t p u l l u p o f f s e t r e s e r v e d m e r g e d m o d e ( * ) = d e f a u l t v a l u e a t p o w e r - u p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 a 1 1 a 1 0 a 9 o c d p d o f f s e t a 8 a 7 a 6 o d t p u o f f s e t a 5 m e r g e d m o d e m e r g e d n o n - m e r g e d ( * ) 0 ( * ) + 1 + 2 + 3 r f u - 3 - 2 - 1 0 ( * ) + 1 + 2 + 3 r f u - 3 - 2 - 1 www.datasheet.co.kr datasheet pdf - http://www..net/
W641GG2JB 1 - gbit gddr 3 graphics sdram publication release date: apr, 22 , 20 11 - 53 - revision a01 - 002 6. 9 extended mode register 3 (emrs3) all functions originally controlled by emrs3 like alternate cl/wr, rdbi , wdbi and multi - cycle preamble (mpr) shall be deleted or deactivated, or shall be permanentely set (autocal enabled, nominal vint). 6.1 0 v endor code and revision id when the vendor code function is enabled by bit a10, the gddr3 graphics sdram will provide the vendor code on dq[3:0] and the revision identification on dq[7:4] as shown in table . the revision id shall be made programmable on a single metal layer ( tbd ). 6. 1 0 .1 vendor id code default revision id (dq7 - dq4) manufacturer id (dq3 - dq0) 0000 1000 www.datasheet.co.kr datasheet pdf - http://www..net/
W641GG2JB 1 - gbit gddr 3 graphics sdram publication release date: apr, 22 , 20 11 - 54 - revision a01 - 002 6. 1 1 b ank / row activation (act) b e f o re a r e ad or wri t e comm a nd c a n be issued to a b a nk, a r o w i n t h at b ank m u st be o p en e d. t h is is accompl i s h ed via the act c o mm a nd, w h ich sel e cts both t h e bank and the row to b e activate d . aft e r o pe n ing a row by iss u ing a n act c o mm a nd, a read c o mma n d may b e issued a f ter t r cd r d to th a t row or a write command a f ter t r c d w r . a subse q ue n t a c t comma n d to a different r o w in t h e same bank can o n ly be issu e d aft e r the pr e v i ous active row h a s been closed ( p r e charg e d). t h e mi n imum t i me interval between successive act com m an d s to t h e same b ank i s defin e d by t r c . a s u bseq u ent act command to a nother b a nk can be issued whi l e the first bank is b e ing acc e ss e d , w h ich resu l t s in a r e duction of total r o w - access over h ead. the min i m u m time interval between successive act commands to act c o mm a nds to ba n ks i n t h e same rank is d e f i ned b y t r r d , and to b anks in d i ffere n t ra n k s by t r r d _ rr ( s e e f i g u r e : bank activation timing on different rank in 2 - cs mode ). t here is a minimum time t r as b e tw e en o p eni n g and cl o s i ng a row. for t h e 1 - cs mo d e (1gb) an ad d it i on a l a ddress bit i s avai l able (a12). i n t e rnal l y t h is ad d ition a l a d dress b i t i s c o nverted into a sel e cti o n si g nal f o r one or the other i n t e rnal r a nk r e presenti n g the first or the seco n d h a lf o f t h e 5 12 mb. s u bse q uent col u mn a cc e sses to the activated b ank are ste e red to the i n ternal r a nk as s e lected by a12 d u ring act i vat i on of the b ank. 6.1 1 .1 activating a specific row c k e c l k # c l k r a s # c s # c a s # w e # a 0 - a 1 1 b a 0 - b a 2 d o n t c a r e r a : r o w a d d r e s s b a : b a n k a d d r e s s b a r a www.datasheet.co.kr datasheet pdf - http://www..net/
W641GG2JB 1 - gbit gddr 3 graphics sdram publication release date: apr, 22 , 20 11 - 55 - revision a01 - 002 6.1 1 .2 bank activation timing 6.1 1 .3 bank activation timing on different rank in 2 - cs mode for e ight b a nk gd d r3 d e vices, th e re may be a ne e d to limit t he n u m b er of activates in a roll i ng w i nd o w to ensure th a t the instantan e ous current su p p lyi n g c a pab i lity of the d e vices i s not exceed e d. to r e fl e ct t h e true cap a bil i ty of the dram instantan e ous c u rr e n t supp l y, the par a m e t e r t f aw (four a c tiv a te win d o w) is d e fine d . no more t h an 4 ba n ks m a y be a ctiv a t e d in a roll i ng t faw window. conve r ting to clocks is done by dividing t faw (n s ) by t ck (ns) and roun d ing u p the n e xt i n t e ger va l ue. as an examp l e o f the roll i ng wi n dow, i f ( t faw / t ck ) rounds up to 10 clocks, and an acti v a te command is issued in clock n, no more than three further activate c o m m ands may be is s u ed in clocks n+1 through n+9. t faw is o n ly v a lid within one rank. there is no furth e r restriction b e tw e en ranks. 6.1 1 .4 four window active tfaw a c t r o w b . x a c t r o w b . y p r e a 8 b . y r / w c o l b . y a c t r o w b . y c l k # a 0 - a 1 1 c l k c o m . b a 0 , b a 1 r o w : r o w a d d r e s s c o l : c o l u m n a d d r e s s b . x : b a n k x b . y : b a n k y r / w : r e a d o r w r i t e c o m m a n d p r e : p r e c h a r g e c o m m a n d a c t : a c t i v a t e c o m m a n d d o n t c a r e t r c d t r a s t r c t r r d a c t r o w b . y r / w c o l b . y p r e a 8 b . y a c t _ 0 r o w b . y a c t _ 1 r o w b . x c l k c l k # a 0 - a 1 1 c o m . b a 0 , b a 1 r o w : r o w a d d r e s s c o l : c o l u m n a d d r e s s b . x : b a n k x b . y : b a n k y r / w : r e a d o r w r i t e c o m m a n d p r e : p r e c h a r g e c o m m a n d a c t _ 0 : a c t i v a t e c o m m a n d r a n k 0 a c t _ 1 : a c t i v a t e c o m m a n d r a n k 1 d o n t c a r e t r c d t r a s t r c t r r d _ r r = 1 a c t a c t a c t a c t a c t a c t a c t a c t t r r d t r r d t r r d t r r d t r r d t r r d t f a w t f a w + 3 * t r r d c l k # c l k c m d d o n t c a r e a c t : a c t i v a t e c o m m a n d www.datasheet.co.kr datasheet pdf - http://www..net/
W641GG2JB 1 - gbit gddr 3 graphics sdram publication release date: apr, 22 , 20 11 - 56 - revision a01 - 002 6.1 1 .5 clock, cke and command / address timings s e t u p an d h o l d t i m i n g f o r ck e i s eq u a l t o cm d a n d a d d r s e t u p an d h o l d tim i ng. 6.1 2 bank activations with refresh 6.1 2 .1 bank activations with refresh command operating mode 2x ref mode bank refreshed per ref c ommand effective tret 1 - cs mode off 4 even or 4 odd banks in all 4 quedrants 32ms on all 8 banks in all 4 quadrants 16ms 2 - cs mode off 4 even or 4 odd banks in selected rank (rank 0 or rank 1) or in both ranks 32ms on all 8 banks in selected rank (rank 0 or rank 1) or in both ranks 16ms c l k # c l k c m d , a d d r , c k e t c k t c h t c l t i p w t i s t i h d o n t c a r e www.datasheet.co.kr datasheet pdf - http://www..net/
W641GG2JB 1 - gbit gddr 3 graphics sdram publication release date: apr, 22 , 20 11 - 57 - revision a01 - 002 6. 1 3 w rites (wr) 6. 1 3 .1 w rite - basic information write b u rsts are i n itiated wi t h a wr comm a nd, as sho w n in f i g u r e . the co l u mn a n d ba n k addr e ss e s are prov i ded with the wr comman d , and auto pr e c h a rge is e ither e na b led or d i sabl e d for th a t access. t he len g th of the burst i n itiated with a wr comma n d is fo u r or e i ght d e pen d ing on the mode r e gister s e tti n g. there is no interruption of wr bursts. the two l east si g n ifica n t ad d ress b its a0 and a1 are Dd o n t c a re. for wr c o mm a nds w i th autopr e c h a rge t h e r o w b e ing accessed i s p rechar g ed t wr/a after the completion of the burst. if t r a s (mi n ) is vi o lated t h e b e gin of t h e i n t e rnal a u t o prech a r g e will be p e rf o rm e d one cycle aft e r t ras ( m in) is m e t . w r, the wri t e recovery t i me f o r write with autopr e c h a rge c a n be progr a m med in the m o de r e gister. cho o s i ng h igh v a lu e s for wr will pr e v e n t the chip to de l ay the i n t e rnal a u t o prech a r g e in ord e r to meet t ra s (min). during wr bursts d a ta will b e reg i ster e d with t h e ed g es of wdqs. the write l a tency can be pro g r a mm e d d u ring exte n ded mode r e gister s e t. the first va l id data is r e gistered with t h e first va l id ris i ng e d ge of w d qs foll o wing t h e wr c o mm a nd. t h e extern a lly pr o v ided wdqs must switch fr o m high to low at t h e b e gin n ing of t h e pre a m b le. there i s also a postamb l e req u irement b e f o re t h e w dqs returns to high. the wdqs sig n al can on l y tra n sition w hen data is a pp l ied at the c h ip in p u t a nd d u r i ng pre - a n d postambl e s. t d q ss is t h e time b e tw e en wr command a nd f i rst valid ris i ng ed g e of wdqs. nomin a l c a se is when w d qs e dg e s are al i gned w i th edg e s of external clk. minimum a nd max i m u m v a lu e s of t dqss d e fine early a nd l a te wdqs op e rat i on. any i n put d a ta will be i g nored before the f i rst va l id risi n g w d qs transiti o n. t dqsl an d t d q sh defi n e the w i dth o f low a n d h igh p h ase of wdqs. t h e sum of t d q sl a n d t dqsh has to b e t c k . b a ck to b a ck w r comm a nds are p o ssible a nd pr o duce a c o ntinu o us f l ow of i n put data. for back to back wr, t c c d has to be met. any wr burst may be foll o wed by a subs e qu e nt rd comma n d . f i g u r e ( w rite followed by read) sho w s the timing req u irements for a wr foll o wed by a rd. in th i s c a s e t h e d el a y b e tw e e n th e w r comman d a n d th e f o llo w i ng rd may be zero for access ac r o ss the two 8 bank seg m ents ( t w t r _ r r = 1 t ck ) as sho w n in f i g u r e ( w rite followed by read on different ranks in 2 - cs mode) . a wr may also be foll o wed by a pre command to the same bank. t w r has to be met as shown in f i g u r e ( w rite followed by precharge on same bank) . setup a n d hold time for i n c o ming dqs and dms rel a t i ve to the wdqs edg e s are spec i f i e d as t d s a n d t dh . dq a nd dm in p u t pu l se wi d th for e a ch i n put is defin e d as t dipw . th e i n pu t d a ta is m a sk e d if the corresp o nd i ng dm si g nal is h i gh. all i m i ng par a m e t e r s are d e f i ned with gra p hics dram t e rm i natio n s o n . www.datasheet.co.kr datasheet pdf - http://www..net/
W641GG2JB 1 - gbit gddr 3 graphics sdram publication release date: apr, 22 , 20 11 - 58 - revision a01 - 002 6.1 3 .1.1 write command 6.1 3 .1.2 mapping of wdqs and dm signal s wdqs d a ta m ask sig n al controll e d dqs wdqs0 dm0 dq0 - dq7 wdqs1 dm1 dq8 - dq15 wdqs2 dm2 dq16 - d q 23 wdqs3 dm3 dq24 - d q 31 a 0 , a 1 a 1 0 - a 1 1 b a 0 , b a 1 c l k # c l k c k e c s # r a s # c a s # w e # a 2 - a 7 , a 9 a 8 c a a p b a d o n t c a r e c a : c o l i m n a d d r e s s b a : b a n k a d d r e s s www.datasheet.co.kr datasheet pdf - http://www..net/
W641GG2JB 1 - gbit gddr 3 graphics sdram publication release date: apr, 22 , 20 11 - 59 - revision a01 - 002 6.1 3 .1.3 basic write burst / dm timing note: w dqs c a n only tr a n sition w h en d a ta is ap p li e d a t the chip i nput and d u ring pr e - a n d postambl e s. d 2 d 1 n o m i n a l w d q s c l k # c l k w d q s d q d m x e a r l y w d q s w d q s w d q s l a t e w d q s t d q s s n o m i n a l d a t a m a s k e d m i n ( t d q s s ) m a x ( t d q s s ) p r e a m b l e p o s t a m b l e d a t a m a s k e d t d q s s t w p r e t d q s h t d q s l t d q s h t d s t d h t d h t d s t d i p w t d s t d h t d i p w t w p s t d o n t c a r e d m x : r e p r e s e n t s o n e d m l i n e d 0 d 3 www.datasheet.co.kr datasheet pdf - http://www..net/
W641GG2JB 1 - gbit gddr 3 graphics sdram publication release date: apr, 22 , 20 11 - 60 - revision a01 - 002 6.1 4 w rite - basic sequence notes : 1. shown w ith n o min a l v a lue of t dqss . 2. wdqs c a n only tr a n sition w h en d a ta is ap p li e d a t the chip i nput and d u ring pr e - a n d postambl e s. 3. wh e n nops are a p pli e d on t h e comm a nd bus, t h e w dqs a n d t h e dq buss e s rema i n sta b le hig h . 4. wh e n dess a r e a ppl i ed on the command b u s, the st a t u s of t h e wdqs a nd dq b u ss e s i s u n know n . c l k # c l k c o m . a d d r . w d q s d q w d q s d q a d d r . c o m . d q d q w d q s w d q s d 0 d 1 d 2 d 3 d 0 d 1 d 2 d 3 n o p n o p n o p n o p n o p n o p n o p n / d w r b / c d 0 d 1 d 2 d 3 d 0 d 1 d 2 d 3 d e s d e s d e s d e s d e s d e s d e s n / d w r b / c 0 1 2 3 4 5 6 7 8 w l = 3 w l = 4 w l = 4 w l = 3 b / c : b a n k / c o l u m n a d d r e s s w r : w r i t e n o p : n o o p e r a t i o n d e s : d e s e l e c t n / d : n o p o r d e s c o m . : c o m m a n d a d d r . : a d d r e s s b / c d # : d a t a t o b / c w l : w r i t e l a t e n c y d o n t c a r e www.datasheet.co.kr datasheet pdf - http://www..net/
W641GG2JB 1 - gbit gddr 3 graphics sdram publication release date: apr, 22 , 20 11 - 61 - revision a01 - 002 6.1 5 w rite - consecutive bursts 6.1 5 .1 gapless bursts 6.1 5 .1.1 gapless write bursts notes : 1. shown w ith n o min a l v a lue of t dqss . 2 . t h e s e con d w r c o mma n d m a y b e e i the r f o r the same ba n k o r a n other ba n k. 3. wdqs c a n only tr a n sition w h en d a ta is ap p li e d a t the chip i nput and d u ring pr e - a n d postambl e s. c o m . a d d r . w r b / c x w d q s d q d y 1 d y 2 d y 3 d y 0 d x 3 d x 2 d x 1 d x 0 d y 1 d y 2 d y 3 d y 0 d x 3 d x 2 d x 1 d x 0 d q n / d w r n / d d e s d e s d e s d e s d e s d e s b / c y w l = 4 w l = 3 0 1 2 3 4 5 6 7 8 9 b / c x : b a n k / c o l u m n a d d r e s s w r : w r i t e d e s : d e s e l e c t n / d : n o p o r d e s c o m . : c o m m a n d a d d r . : a d d r e s s b / c d x # : d a t a t o b / c x w l : w r i t e l a t e n c y d o n t c a r e b / c y : b a n k / c o l u m n a d d r e s s d y # : d a t a t o b / c y c l k # c l k w d q s www.datasheet.co.kr datasheet pdf - http://www..net/
W641GG2JB 1 - gbit gddr 3 graphics sdram publication release date: apr, 22 , 20 11 - 62 - revision a01 - 002 6.1 5 .2 b ursts with gaps 6.1 5 .2.1 consecutive write bursts with gaps notes : 1. shown w ith n o min a l v a lue of t dqss . 2 . t h e s e con d w r c o mma n d m a y b e e i the r f o r the same ba n k o r a n other ba n k. 3. wdqs c a n only tr a n sition w h en d a ta is ap p li e d a t the chip i nput and d u ring pr e - a n d postambl e s. c o m . a d d r . w r b / c x w d q s d q d y 1 d y 2 d y 3 d x 3 d x 2 d x 1 d x 0 d y 1 d y 2 d y 3 d y 0 d x 3 d x 2 d x 1 d x 0 d q n / d n / d w r n / d d e s d e s d e s d e s d e s b / c y w l = 4 w l = 3 0 1 2 3 4 5 6 7 8 9 b / c x : b a n k / c o l u m n a d d r e s s w r : w r i t e d e s : d e s e l e c t n / d : n o p o r d e s c o m . : c o m m a n d a d d r . : a d d r e s s b / c d x # : d a t a t o b / c x w l : w r i t e l a t e n c y d o n t c a r e b / c y : b a n k / c o l u m n a d d r e s s d y # : d a t a t o b / c y c l k # c l k w d q s d y 0 1 0 d e s www.datasheet.co.kr datasheet pdf - http://www..net/
W641GG2JB 1 - gbit gddr 3 graphics sdram publication release date: apr, 22 , 20 11 - 63 - revision a01 - 002 6. 1 5 .3 w rite with autoprecharge notes : 1. shown w ith n o min a l v a lue of t dqss . 2 . t wr/a starts a t the f i rst rising e dge of clk aft e r the last valid e dge of wdqs. 3 . t r p st a rts aft e r t wr/a has b e en exp i r e d. 4. wh e n issui n g a w r/a comma n d p le a se c o nsid e r that t h e t ras requ i rement a lso must be met at the b e gin n ing o f t r p . 5 . t wr/a t wr . 6. wdqs c a n only tr a n sition w h en d a ta is ap p li e d a t the chip i nput and d u ring pr e - a n d postambl e s. c o m . a 9 , a 7 - a 2 w r / a b / c n / d d e s d e s d e s d e s d e s d e s d e s d e s 0 1 2 3 4 5 6 7 8 9 c l k # c l k 1 0 d e s d 3 d 2 d 1 d 0 d q d e s : d e s e l e c t n / d : n o p o r d e s c o m . : c o m m a n d a d d r . : a d d r e s s b / c w r / a : w r i t e w i t h a u t o - p r e c h a r g e w l : w r i t e l a t e n c y d o n t c a r e b / c : b a n k / c o l u m n a d d r e s s d # : d a t a t o b / c d 1 d 2 d 3 d 0 w l = 4 w l = 3 t r a s m i n s a t i s i f e d b e g i n o f a u t o p r e c h a r g e b e g i n o f a u t o p r e c h a r g e t r a s m i n s a t i s i f e d t w r / a = 3 t w r / a = 3 t r p t r p d q a 8 w d q s w d q s www.datasheet.co.kr datasheet pdf - http://www..net/
W641GG2JB 1 - gbit gddr 3 graphics sdram publication release date: apr, 22 , 20 11 - 64 - revision a01 - 002 6. 1 5 .4 w rite followed by read notes : 1. shown w ith n o min a l v a lue of t dqss . 2. t h e rd c o mm a nd may b e either f o r the same b a nk o r a nother ba n k. 3. wdqs c a n only tr a n sition w h en d a ta is ap p li e d a t the chip i nput and d u ring pr e - a n d postambl e s. w r b / c n / d d e s d e s d e s d e s d e s d e s r d n / d w l = 3 0 1 2 3 4 5 6 7 8 9 c l k # c l k d 1 d 2 d 3 d 0 t w t r w r b / c n / d d e s d e s d e s d e s d e s d e s d e s r d b / c d 3 d 2 d 1 d 0 b / c w l = 4 d q w d q s d q w d q s c o m . a d d r . c o m . a d d r . d e s : d e s e l e c t n / d : n o p o r d e s c o m . : c o m m a n d a d d r . : a d d r e s s b / c w l : w r i t e l a t e n c y d o n t c a r e b / c : b a n k / c o l u m n a d d r e s s d # : d a t a t o b / c r d : r e a d w r : w r i t e t w t r www.datasheet.co.kr datasheet pdf - http://www..net/
W641GG2JB 1 - gbit gddr 3 graphics sdram publication release date: apr, 22 , 20 11 - 65 - revision a01 - 002 6. 1 5 .5 w rite followed by read on different ranks in 2 - cs mode notes : 1 . t w t r _ r r i s d e f i ned b e tw e en write and re a d comm a nd on d i ffere n t rank. 2. shown w ith n o min a l v a lue of t dqss . 3. t h e rd c o mm a nd may b e either f o r the same b a nk o r a nother ba n k. 4. wdqs c a n only tr a n sition w h en d a ta is ap p li e d a t the chip i nput and d u ring pr e - a n d postambl e . d e s d 3 d 2 d 1 d 0 d 3 d 2 d 1 d 0 d 3 d 2 d 1 d 0 d 3 d 2 d 1 d 0 c l k # c l k c o m . a d d r . d q w d q s r d q s c o m . a d d r . w d q s r d q s d q 0 1 2 3 4 5 1 1 1 2 1 3 6 7 1 4 1 5 d e s : d e s e l e c t n / d : n o p o r d e s c o m . : c o m m a n d a d d r . : a d d r e s s b / c w l : w r i t e l a t e n c y d o n t c a r e b / c : b a n k / c o l u m n a d d r e s s d # : d a t a t o b / c r d _ 1 : r e a d o n r a n k 1 w r _ 0 : w r i t e o n r a n k 0 d e s d e s d e s d e s d e s d e s d e s d e s d e s n / d r d w r w r _ 0 r d _ 1 n / d d e s d e s d e s d e s d e s d e s d e s d e s d e s b / c b / c b / c b / c w l = 3 w l = 4 c l = 9 t w t r _ r r = 1 t w t r _ r r = 1 c l = 9 d e s www.datasheet.co.kr datasheet pdf - http://www..net/
W641GG2JB 1 - gbit gddr 3 graphics sdram publication release date: apr, 22 , 20 11 - 66 - revision a01 - 002 6. 1 5 .6 w rite followed by dterdis notes : 1. shown w ith n o min a l v a lue of t dqss . 2. wdqs c a n only tr a n sition w h en d a ta is ap p li e d a t the chip i nput and d u ring pr e - a n d postambl e s. 3. a marg i n of o n e c l ock h a s b e en introd u ced in ord e r to m a ke sure that the d a ta termin a t i on a r e st i ll on when the l a st write data reac h e s the memory. 4. t h e m i nimum distance b e tw e en wr i t e a n d dterdis is o ne clock. w r b / c w l = 3 0 1 2 3 4 5 6 7 8 9 c l k # c l k d 1 d 2 d 3 d 0 w r b / c d 3 d 2 d 1 d 0 w l = 4 d q w d q s d q w d q s c o m . a d d r . c o m . a d d r . d e s : d e s e l e c t n / d : n o p o r d e s e l e c t c o m . : c o m m a n d a d d r . : a d d r e s s b / c w l : w r i t e l a t e n c y d o n t c a r e b / c : b a n k / c o l u m n a d d r e s s d # : d a t a t o b / c c l : c a s l a t e n c y w r : w r i t e d t d : d t e r d i s d a t a t e r m i n a t i o n o f f c l = 7 c l = 7 d t d d e s d e s d e s d e s d e s d e s d e s d e s d e s d e s d e s d e s d e s d e s d e s d e s d e s d t d n / d 1 0 w r www.datasheet.co.kr datasheet pdf - http://www..net/
W641GG2JB 1 - gbit gddr 3 graphics sdram publication release date: apr, 22 , 20 11 - 67 - revision a01 - 002 6. 1 5 .7 w rite with autoprecharge followed by read / read with autoprecharge on another bank notes : 1. shown w ith n o min a l v a lue of t dqss . 2. t h e rd c o mm a nd is only al l o wed for an o t h er a ctiv a t e d bank. 3 . t wr/a i s s e t t o 4 i n t h i s ex a m p l e. 4. wdqs c a n only tr a n sition w h en d a ta is ap p li e d a t the chip i nput and d u ring pr e - a n d postambl e s. w r / a b / c n / d d e s d e s d e s d e s d e s d e s r d r d / a d e s w l = 3 0 1 2 3 4 5 6 7 8 9 c l k # c l k d 1 d 2 d 3 d 0 t w t r w r / a b / c n / d d e s d e s d e s d e s d e s d e s d e s r d r d / a b / c d 3 d 2 d 1 d 0 b / c w l = 4 d q w d q s d q w d q s c o m . c o m . a 8 d e s : d e s e l e c t n / d : n o p o r d e s e l e c t c o m . : c o m m a n d a d d r . : a d d r e s s b / c w l : w r i t e l a t e n c y d o n t c a r e b / c : b a n k / c o l u m n a d d r e s s d # : d a t a t o b / c r d r d / a : r e a d o r r e a d w i t h a u t o p r e c h a r g e w r / a : w r i t e w i t h a u t o p r e c h a r g e t w t r 0 : r d , 1 : r d / a a 9 , a 2 - a 7 a 8 a 9 , a 2 - a 7 t w r / a t r p t w r / a t w t r t r p b e g i n o f a u t o p r e c h a r g e b e g i n o f a u t o p r e c h a r g e www.datasheet.co.kr datasheet pdf - http://www..net/
W641GG2JB 1 - gbit gddr 3 graphics sdram publication release date: apr, 22 , 20 11 - 68 - revision a01 - 002 6. 1 5 .8 w rite followed by precharge on same bank notes : 1. shown w ith n o min a l v a lue of t dqss . 2. wr a n d p r e comman d s a r e to same ba n k. 3 . t r as req u irement must a l so b e m e t before iss u ing pre comm a nd. 4. wdqs c a n only tr a n sition w h en d a ta is ap p li e d a t the chip i nput and d u ring pr e - a n d postambl e s. c o m . a d d r . w r b / c n / d d e s d e s d e s d e s d e s d e s d e s p r e 0 1 2 3 4 5 6 7 8 9 c l k # c l k 1 0 d e s w l = 3 d 1 d 2 d 3 d 0 t w t r w r b / c n / d d e s d e s d e s d e s d e s d e s d e s d e s d 3 d 2 d 1 d 0 w l = 4 d q w d q s d q w d q s c o m . a d d r . d e s : d e s e l e c t n / d : n o p o r d e s e l e c t c o m . : c o m m a n d a d d r . : a d d r e s s b / c w l : w r i t e l a t e n c y d o n t c a r e b / c : b a n k / c o l u m n a d d r e s s p r e : p r e c h a r g e d x # : d a t a t o b / c x w r : w r i t e t w t r d y # : d a t a t o b / c y t r p t r p p r e b b www.datasheet.co.kr datasheet pdf - http://www..net/
W641GG2JB 1 - gbit gddr 3 graphics sdram publication release date: apr, 22 , 20 11 - 69 - revision a01 - 002 6. 1 6 r e ads (rd) 6. 1 6 .1 read - basic information read b u rsts a re i n itiated with a r d comma n d , as s h own in f i g u r e ( basic read burst timing) . the co l u mn a n d ba n k addr e ss e s are prov i ded with t h e rd command a n d autopre ch a rge is e i t h er ena b led o r disa b led for th a t a c c e ss. the l ength o f the burst in i t i a t e d w i th a rd comma n d is 4 o r 8. th e re is no interru p t i on of rd bursts. t h e two l e ast si g n ificant st a r t ad d r e ss b i ts are Ddo n t care. if a u to p rechar g e i s e n abl e d , the row bei n g a ccessed will start internal pr e charge at the latter o f either t h e c o m p letion of b its prefetch o r o ne cyc l e after t r as(min) is m e t. during rd bursts t h e memory d e vice drives the read d a ta edge ali g ned w i th the rdqs si g nal w h ich is also d riven b y the m e m o ry. aft e r a progr a m ma b le c as l a t e ncy of 7, 8, 9 or 10 the d a ta is driven to the co n t ro l ler. r d qs l eaves high st a t e one cycle before its f i r s t r i sing ed g e (rd pre a mble t r pre ). after the l a st f a lli n g e d ge of rdqs a p o stamb l e o f t rpst is performed. t ac is the time b e t w een t h e p o sitive e dge of c l k and the app e arance of the corres p ond i ng driven re a d d a ta. the skew betwe e n r dqs and t h e cr o s s i ng poi n t of c l k / c l k # is s p ecified as t dqsck . t ac a n d t d q s c k are d e fin e d relative l y to the p o sitive e dge of c l k. t d q sq i s the sk e w b e tween a rdqs edge a n d the last va l id data e dge b e lon g ing to the rdqs edg e . t dqsq is d e rived at e a ch rdqs e d ge a nd beg i ns w i th rdqs tr a n sition a n d e nds with the l a st val i d trans i t i o n of dqs. t q h s i s the d a ta ho l d skew fact o r a nd t qh is the time f r om the first v a lid risi n g ed g e of rdqs to the first co n f o r m i ng dq goi n g n o n - valid and it dep e nds on t h p a n d t qhs . t hp is the m i nimum of t c l a n d t c h . t q h s i s eff e ctive l y the t i me from t h e first data transiti o n (before rd q s) to the r dqs transiti o n. th e d a ta v a lid w i nd o w is d e riv e d f o r ea ch r d q s t ra n siti o n and is defi n ed as t q h minus t dqs q . after compl e ti o n of a burst, a ss u ming n o other comman d s have been i n it i a ted, d a ta will go high and rdqs will go high. back to back rd comm a nds a r e possi b le p roduc i ng a c o ntinu o us f l ow of o u t p ut d a t a . f o r b a ck to b a ck rd, t ccd h a s t o b e me t. a n y rd burst m a y b e foll o wed b y a s u bse q uent wr c o mm a nd. the m i nimum r e quir e d n u mber of nop c o mm a nds betwe e n t h e rd comm a nd a n d t h e wr command ( t rtw ) d epe n ds on the p r o g rammed cas l a t e ncy and the programmed w rite l a tency t rt w (m i n ) = (cl+4 - w l ) , the timing req u ireme n ts f o r rd foll o wed by a w r with s o me c o m b inati o ns o f cl a n d wl. a r d m a y a lso be fol l owed by a pre c o mm a nd. s i nce no interru p t i o n of b u rsts is a llo w ed the mi n imum time b e tw e en a rd command and a pre is t w o clock cycles . all timing parameters are d e fined with control l er t e rm i natio n s on. www.datasheet.co.kr datasheet pdf - http://www..net/
W641GG2JB 1 - gbit gddr 3 graphics sdram publication release date: apr, 22 , 20 11 - 70 - revision a01 - 002 6. 1 6 . 1.1 read command c k e c l k # c l k r a s # c s # c a s # w e # a 2 - a 7 , a 9 a 0 , a 1 a 1 0 - a 1 1 d o n t c a r e a p : a u t o p r e c h a r g e c a : r o w a d d r e s s b a : b a n k a d d r e s s c a a p b a a 8 b a 0 - b a 2 www.datasheet.co.kr datasheet pdf - http://www..net/
W641GG2JB 1 - gbit gddr 3 graphics sdram publication release date: apr, 22 , 20 11 - 71 - revision a01 - 002 6. 16 . 1.2 basic read burst timing notes : 1. t h e gddr3 graphics sdram swit c h es o f f the dq termin a t i ons one cycle b e fore data a p pears on the b u s a nd driv e s the d a ta b u s high. 2. the gddr3 graphics sdram drives the data bus high one cycle after the last data d r iven on the bus bef o r e switching the t e rm i nation o n aga i n. c l k # c l k r d q s d q ( f i r s t d a t a v a l i d ) d q ( l a s t d a t a v a l i d ) a l l d q s c o l l e c t i v e l y t d q s c k t a c t q h t l z t q h s t d q s q t h z d 3 d 3 d 3 d 2 d 2 d 2 d 1 d 1 d 1 d 0 d 0 d 0 t d q s q t c k t h p t c h t c l t r p s t d a t a v a l i d w i n d o w d o n t c a r e h i - z : n o t d r i v e n b y d d r s g r a m t r p r e p r e a m b l e p o s t a m b l e www.datasheet.co.kr datasheet pdf - http://www..net/
W641GG2JB 1 - gbit gddr 3 graphics sdram publication release date: apr, 22 , 20 11 - 72 - revision a01 - 002 6. 16.2 read - basic sequence 6. 16 . 2. 1 read burst notes : 1. shown w ith n o min a l t ac and t d q s q . 2. rdqs w i ll st a r t drivi n g high 1 / 2 cycle pri o r to t h e f i rst f a lli n g edge a nd st o p 1/2 c ycle a f ter t h e last ris i ng ed g e of r d qs. 3. t h e dq term i natio n s a r e sw i t c h ed off 1 cycle before the f i rst re a d data and on a gain 1 cycle after the l a st r e ad data. c o m . a d d r . c l k # c l k d q r d q s 0 1 2 3 6 7 8 9 1 0 d 0 c a s l a t e n c y = 6 c a s l a t e n c y = 5 r d b / c n / d n / d n / d n / d n / d n / d n / d n / d n / d d 1 d 2 d 3 d 0 d 1 d 2 d 3 r d q s d q n / d : n o p o r d e s e l e c t c o m . : c o m m a n d a d d r . : a d d r e s s b / c d o n t c a r e b / c : b a n k / c o l u m n a d d r e s s d x : d a t a f r o m b / c r d : r e a d d q s : t e r m i n a t i o n s o f f r d q s : n o t d r i v e n 1 1 www.datasheet.co.kr datasheet pdf - http://www..net/
W641GG2JB 1 - gbit gddr 3 graphics sdram publication release date: apr, 22 , 20 11 - 73 - revision a01 - 002 6. 16.3 consecutive read bursts 6. 16 . 3. 1 gapless bursts 6. 16 . 3 .1 .1 gapless consecutive read bursts notes : 1. t h e s e cond rd command may be e i t h er for the same bank or an o t h er b ank. 2. shown w ith n o min a l t ac and t d q s q . 3. example a p pl i e s o n ly when r e ad comman d s a r e i ss u ed to s a me d e vice. 4. rdqs w i ll st a r t drivi n g high 1 / 2 cycle pri o r to t h e f i rst f a lli n g edge a nd st o p 1/2 c ycle a f ter t h e last ris i ng ed g e of r d qs. 5. t h e dq term i natio n s a r e sw i t c h ed off 1 cycle before the f i rst re a d data and on a gain 1 cycle after the l a st r e ad data. c o m . a d d r . c l k # c l k r d q s 0 1 2 3 6 7 8 9 1 0 c a s l a t e n c y = 5 r d b / c x n / d r d n / d n / d n / d n / d n / d n / d n / d 1 1 d q d x 0 c a s l a t e n c y = 6 d x 1 d x 2 d x 3 r d q s d q n / d : n o p o r d e s e l e c t c o m . : c o m m a n d a d d r . : a d d r e s s b / c d o n t c a r e b / c x : b a n k / c o l u m n a d d r e s s d x # : d a t a f r o m b / c x r d : r e a d d q s : t e r m i n a t i o n s o f f r d q s : n o t d r i v e n 1 2 1 3 b / c y : b a n k / c o l u m n a d d r e s s d y # : d a t a f r o m b / c y n / d n / d b / c y d y 0 d y 1 d y 1 d y 0 d x 3 d x 2 d x 1 d x 0 d y 2 d y 3 d y 3 d y 2 www.datasheet.co.kr datasheet pdf - http://www..net/
W641GG2JB 1 - gbit gddr 3 graphics sdram publication release date: apr, 22 , 20 11 - 74 - revision a01 - 002 6. 16.4 b ursts with gaps 6. 16 . 4. 1 consecutive read bursts with gaps notes : 1. t h e s e cond rd command may be e i t h er for the same bank or an o t h er b ank. 2. rdqs w i ll st a r t drivi n g high 1 / 2 cycle pri o r to t h e f i rst f a lli n g edge a nd st o p 1/2 c ycle a f ter t h e last ris i ng ed g e of r d qs. 3. t h e dq term i natio n s a r e sw i t c h ed off 1 cycle before the f i rst re a d data and on a gain 1 cycle after the l a st r e ad data. c o m . a d d r . c l k # c l k d q d q r d q s 0 1 2 3 6 7 8 9 1 0 1 1 1 2 r d q s c o m . : c o m m a n d a d d r . : a d d r e s s b / c d o n t c a r e b / c x : b a n k / c o l u m n a d d r e s s x d x # : d a t a f r o m b / c x r d : r e a d d q s : t e r m i n a t i o n s o f f r d q s : n o t d r i v e n b / c y : b a n k / c o l u m n a d d r e s s y d y # : d a t a f r o m b / c y c a s l a t e n c y = 6 c a s l a t e n c y = 5 r d b / c x n / d d x 0 n / d n / d b / c y r d n / d n / d n / d n / d n / d n / d d x 1 d x 2 d x 3 d x 0 d x 1 d x 3 d x 2 d y 0 d y 1 d y 3 d y 2 d y 0 d y 1 d y 2 www.datasheet.co.kr datasheet pdf - http://www..net/
W641GG2JB 1 - gbit gddr 3 graphics sdram publication release date: apr, 22 , 20 11 - 75 - revision a01 - 002 6. 16.5 read followed by dterdis notes : 1. at l e ast bl/2+1 nops are re q u ired b e t w een a read command a n d a dterdis comm a nd in or d e r to avo i d c o ntention o n t h e rdqs bus in a 2 memories system. 2. cas l a tency 7 is u sed as an examp l e. 3. the dq ter m inations a r e switched o f f (cl - 1) clock periods after the dterdis command for a duration of bl/2+2 clocks. 4. t h e dash e d lin e s (rdqs b u s) d e scribe the rdqs b eh a v i or in t h e c a se where the dterdis command c o rr e s p on d s to a read co m mand applied to the second graphics dram in a 2 memories syste m . in this case, rdqs would be d r iven by t h e second grap h ics d r am. www.datasheet.co.kr datasheet pdf - http://www..net/
W641GG2JB 1 - gbit gddr 3 graphics sdram publication release date: apr, 22 , 20 11 - 76 - revision a01 - 002 6. 16.6 read with autoprecharge notes : 1. wh e n issui n g a r d/a comman d , t h e t r as req u irement m u st be met a t the be g in n ing of aut o prech a rge . 2. shown w ith n o min a l t ac and t d q sq 3. rdqs w i ll st a r t drivi n g high 1 / 2 cycle pri o r to t h e f i rst f a lli n g edge a nd st o p 1/2 c ycle a f ter t h e last ris i ng ed g e of r d qs. 4. t h e dq term i natio n s a r e sw i t c h ed off 1 cycle before the f i rst re a d data and on a gain 1 cycle after the l a st r e ad data. 5 . t r as lock o ut su p port. www.datasheet.co.kr datasheet pdf - http://www..net/
W641GG2JB 1 - gbit gddr 3 graphics sdram publication release date: apr, 22 , 20 11 - 77 - revision a01 - 002 6. 16.7 read followed by write notes : 1. shown w ith n o min a l t a c , t dqsq a n d t dqss . 2. rdqs w i ll st a r t drivi n g high 1 / 2 cycle pri o r to t h e f i rst f a lli n g edge a nd st o p 1/2 c ycle a f ter t h e last ris i ng ed g e of r d qs. 3. t h e dq term i natio n s a r e sw i t c h ed off 1 cycle before the f i rst re a d data and on a gain 1 cycle after the l a st r e ad data . 4. wdqs c a n only tr a n sition w h en d a ta is ap p li e d a t the chip i nput and d u ring pr e - a n d postambl e s. 5. t h e write comm a nd may be either on the same b a nk o r on a nother b a nk. www.datasheet.co.kr datasheet pdf - http://www..net/
W641GG2JB 1 - gbit gddr 3 graphics sdram publication release date: apr, 22 , 20 11 - 78 - revision a01 - 002 6. 16.8 read followed by p r echarge on the same bank notes : 1 . t r as req u irement must a l so b e m e t before iss u ing pre comm a n d . 2. rd and pre commands are a p pli e d to the same b a nk. 3. shown w ith n o min a l t ac and t d q sq . 4. rdqs w i ll st a r t drivi n g high 1 / 2 cycle pri o r to t h e f i rst f a lli n g edge a nd st o p 1/2 c ycle a f ter t h e last ris i ng ed g e of r d qs. www.datasheet.co.kr datasheet pdf - http://www..net/
W641GG2JB 1 - gbit gddr 3 graphics sdram publication release date: apr, 22 , 20 11 - 79 - revision a01 - 002 6. 17 data termination disable (dterdis) the data temination disable command is detected by the device by snooping the bus for read commands when cs is high. the terminators a re d i sabl e d starting at cl - 1 cl o cks af t e r t h e dterdis c o mm a nd is d e t e c t ed an d t h e d u r a ti o n is 4 clocks. the command and ad d ress ter m inators are always ena b le d . dterdis may only be app l ied to the gddr3 graph i cs m e m o r y i f i t i s n o t i n t h e pow e r d ow n o r i n t h e sel f refresh state. the timing re l a tions h ip betwe e n dter d i s and oth e r c o mm a nds i s d e fi n ed by the constrai n t to avo i d c o nt e n tion on the rdqs b u s (i.e r ead to dterdis tr a n sitio n ) or the necessity to have a d e f i ned termi n a t i on on t h e data b u s duri n g w rite (i.e. w rite to dte r dis tr a n sitio n ). a c t and p r e/preall m a y b e ap p li e d at any time before o r after a dterdis comm a nd. 6. 17 .1 data terminal disable command www.datasheet.co.kr datasheet pdf - http://www..net/
W641GG2JB 1 - gbit gddr 3 graphics sdram publication release date: apr, 22 , 20 11 - 80 - revision a01 - 002 6 17 . 1.1 dterdis timing www.datasheet.co.kr datasheet pdf - http://www..net/
W641GG2JB 1 - gbit gddr 3 graphics sdram publication release date: apr, 22 , 20 11 - 81 - revision a01 - 002 6. 17 . 2 dterdis followed by dterdis notes : 1. at l e ast 1nop is r e quir e d b e tween 2 dterdis c o mma n ds. t h is correspo n d to a r e ad to r ead transition o n t h e ot h e r memory in a 2 memo r i es system. 2. cas l a tency 7 is u sed as an examp l e. 3. the dq ter m inations a r e switched o f f (cl - 1) clock periods after the dterdis command for a duration of 4 clocks. 4. t h e dash e d lin e s (rdqs b u s) d e scribe the rdqs b eh a v i or in t h e c a se where the dterdis command c o rr e s p on d s to a read co m mand applied to the second graphics dram in a 2 memories syste m . in this case, rdqs would be d r iven by t h e second grap h ics d r am. www.datasheet.co.kr datasheet pdf - http://www..net/
W641GG2JB 1 - gbit gddr 3 graphics sdram publication release date: apr, 22 , 20 11 - 82 - revision a01 - 002 6. 17 . 3 dterdis followed by read notes : 1. at l e ast bl/2+1 nops are re q u ired b e t w een a dterdis comma n d a nd a read comm a nd in or d e r to avo i d c o ntention o n t h e rdqs bus in a 2 memories system. 2. cas l a tency 7 is u sed as an examp l e. 3. the dq ter m inations a r e switched o f f (cl - 1) clock periods after the dterdis command for a duration of 4 clocks. www.datasheet.co.kr datasheet pdf - http://www..net/
W641GG2JB 1 - gbit gddr 3 graphics sdram publication release date: apr, 22 , 20 11 - 83 - revision a01 - 002 6. 17 . 4 dterdis followed by write notes : 1. write sho w n w ith n o min a l v a lue of t d q ss . 2. wdqs c a n only tr a n sition w h en d a ta is ap p li e d a t the chip i nput and d u ring pr e - a n d postambl e s . 3. the m i nimum distance between dterdis and write is ( c l - wl + bl/2 +2) clocks. www.datasheet.co.kr datasheet pdf - http://www..net/
W641GG2JB 1 - gbit gddr 3 graphics sdram publication release date: apr, 22 , 20 11 - 84 - revision a01 - 002 6. 18 precharge (pre/preall) the pr e charge c o mma n d is used to d eactivate the o p en row in a particu l a r b ank (pre) o r the o pen rows in a ll ba n ks (p r e a l l). the ba n k(s) w i ll e n t e r t h e id l e state a n d be avai l able aga i n for a n e w r o w access after t h e t i me t r p . a8/ap s a mpled with the p r e comm a nd d e termines w hether o ne o r all banks are to b e pr e charg e d. f o r pre comman d s ba0, ba1 a nd ba2 sel e ct t h e ba n k. for preall inputs ba0, ba1 and ba2 are Ddo n t care. the pre/prea l l command m a y not b e given u n less t h e t r as req u irement is m e t f o r the s e lected ba n k (p r e), o r f o r all ba n ks within o n e ra n k ( p r e a l l ). 6. 18 .1 precharge command www.datasheet.co.kr datasheet pdf - http://www..net/
W641GG2JB 1 - gbit gddr 3 graphics sdram publication release date: apr, 22 , 20 11 - 85 - revision a01 - 002 6. 18 .2 ba2, ba1 and ba0 precha r ge bank selection within one rank a8 / ap ba2 b a1 b a0 p r echarged bank(s) 0 0 0 0 b a n k 0 o n ly 0 0 0 1 b a n k 1 o n ly 0 0 1 0 b a n k 2 o n ly 0 0 1 1 b a n k 3 o n ly 0 1 0 0 b a n k 4 o n ly 0 1 0 1 b a n k 5 o n ly 0 1 1 0 b a n k 6 o n ly 0 1 1 1 b a n k 7 o n ly 1 x x x a l l b an ks wit h in o n e r an k 6. 18 .3 precharge timing www.datasheet.co.kr datasheet pdf - http://www..net/
W641GG2JB 1 - gbit gddr 3 graphics sdram publication release date: apr, 22 , 20 11 - 86 - revision a01 - 002 6. 19 auto refresh command (aref) a r ef is used to do a refresh cycle on one row in each bank. the a ddresses are g e nerated b y an i n ternal refresh c o ntroll e r; external a d dress p ins are Ddon t care. all banks w ithin t h e ra n k s m u st b e i d le before the aref c o mm a nd can be app l ie d . the d e lay betwe e n the aref c o mm a nd and the next act or subse q uent a r ef m u st be at least t rf c (min). the refresh peri o d starts when the aref c o mm a nd is e n tered a nd e nds t r f c l a ter at which t i me all banks wi l l b e in t h e idle state. within a peri o d o f t ref t h e w h ole memory h a s to be refresh e d. the avera g e p e r i od i c interval time from aref to aref i s th e n t r e f i . to improve eff i ciency bursts of aref comman d s can be used. such bursts m a y consist of maximum 8 aref c o mm a nds. t r f c (min ) i s t h e min i m u m r e qu i r e d tim e b et w een two aref comma n d s i n side of o ne aref burst. accordi n g to the numb e r of a r ef comman d s in o n e b u rst the a v e rage r e qu i r e d t i me from one aref burst to the next can be increas e d . exampl e : if the a r ef bursts consists of 8 aref c o mm a nds, t h e aver a ge time from one aref b u rst to the next i s 8 * t r e fi . the aref command ge n erates a n u pd a te of the ocd o u t p ut imped a nce and o f the ad d resses, comman d s a nd dq te rminations. the t i ming parameter t ko . a r ef aff e cts one r a nk, o n ly. t h e r e f o re, a c c e ss e s to the oth e r r a nk in t h e 2 - cs - m o de are a l low e d after t ko has exp i r e d. 6. 19 .1 auto refresh command www.datasheet.co.kr datasheet pdf - http://www..net/
W641GG2JB 1 - gbit gddr 3 graphics sdram publication release date: apr, 22 , 20 11 - 87 - revision a01 - 002 6. 19 .2 auto refresh cycle 6. 20 self - refresh 6. 20 . 1 s elf - refresh entry (srefen) the self - refresh m o de c a n be used to retain data i n the gddr3 graphics r a m even if the r e st of the system is pow e r e d d o wn. w h en in t h e se l f - refresh m o de, the gddr3 gra p hics ram retai n s d a ta w it h out ext e rnal clock i ng. t h e s e lf - refresh comm a nd is initi a t e d l ike an auto - refresh c o mm a nd exc e pt cke is disa b led ( l o w ). se l f r e fr e sh entry is o n ly p o ssib l e i f all b a nks are prec h a rged a n d t rp is m e t . t h e gdd r 3 gr a ph i c s ra m ha s a bui l d - i n t i m e r t o accommod a te s e lf - refresh o p eratio n . t h e self - refresh c o mm a nd i s defin e d b y hav i ng c s # , ra s # , ca s # a n d c k e he l d l o w w ith w e # high at t h e risi n g ed g e of the c l ock. once the comm a nd i s r e gistere d , cke must be he l d lo w to keep the dev i c e i n s e lf - refresh m o de. wh e n t h e gd d r3 gra p hics ram h a s entered the self - refresh m o de, a l l e x ter n al c o ntr o l si g nals, exc e pt cke a r e d isab l ed. f o r pow e r sav i ng, the d ll and the cl o ck are i n t e rnal l y dis a ble; a n d the ad d r e ss and command terminators a r e turned off. b ut the data terminators remain on. t h e user may h a lt t h e extern a l clock w h ile the dev i c e is in s e lf - refresh mode t h e n e xt cl o ck after s e lf - r e f r e sh entry, how e v e r the c l ock must be restarted before the d e vice can exit se l f - r e f r e sh o perati o n. in 2 - cs - mod e , sr may only be entered for b o th ra n ks in para l lel. ther e f ore cs0# a nd cs1# w i ll h a ve to be s e t to low leve l . www.datasheet.co.kr datasheet pdf - http://www..net/
W641GG2JB 1 - gbit gddr 3 graphics sdram publication release date: apr, 22 , 20 11 - 88 - revision a01 - 002 6. 20 . 1.1 self - refresh entry command www.datasheet.co.kr datasheet pdf - http://www..net/
W641GG2JB 1 - gbit gddr 3 graphics sdram publication release date: apr, 22 , 20 11 - 89 - revision a01 - 002 6. 20 . 1.2 self refresh entry 6. 21 self - refresh exit (srefex) to exit t h e s e lf r e fresh mod e , a st a b le extern a l c l ock i s nee d ed b e fore setting cke hi g h asynchro n ously. once the s e lf - refresh exit c o m m and is re g ist e red, a d e lay e q ual o r lon g er th a n t xsrd must b e s a t i sfi e d b e fore a r e ad command c a n be a ppl i ed. during t h is time, the dll i s a u tomatical l y ena b le d , reset a nd cal i brated. cke must remain high for the entire self - refresh exit period and commands must be gated off with cs # held high. alternately, nop comm a nds may b e reg i ster e d on each positive clock ed g e duri n g t h e s e lf r e fresh e x i t i n terv a l. www.datasheet.co.kr datasheet pdf - http://www..net/
W641GG2JB 1 - gbit gddr 3 graphics sdram publication release date: apr, 22 , 20 11 - 90 - revision a01 - 002 6. 21 .1 self refresh exit command 6. 21 .2 self refresh exit www.datasheet.co.kr datasheet pdf - http://www..net/
W641GG2JB 1 - gbit gddr 3 graphics sdram publication release date: apr, 22 , 20 11 - 91 - revision a01 - 002 6. 22 power - down the gddr3 re q u ires cke to b e act i ve a t a l l times an a c c e ss is in pro g r e ss: from the issui n g of a read o r wri t e c o mm a nd u n t i l comp l e tion o f the burst. for reads, a b u rst c o mpleti o n is d e f i ned aft e r the rising ed g e of the r ead p o st a m b le. f o r wr i t e s , a burst comp l e tion is d e fi n ed one c l ock a f ter t h e rising e d ge of the w rite p o st a m b le. for r e ad w ith autoprec h a rge a nd w rite with a u to p rechar g e , the i n ter n al a u to p rechar g e must be c o mpleted before entering p o wer - dow n . p o wer - do w n is entered w h en cke is registered l o w . (no access c a n be in pro g ress. "access" means as we l l r ead o r write to a sec o nd mem o ry s h aring the d a ta b u s in a d ual r a nk syst e m .) if po w e r - down occurs when all banks a r e id l e , this mode is referred to as pre c h a r g e p o w e r - dow n ; if p o w e r - down occurs wh e n th e re is a row active in a n y b ank, th i s m o de is referred to a s act i ve pow e r - down. e n t e r i ng pow e r - down de a ctiv a t e s t h e i n put a n d o u t p ut buffers, exclu d ing clk, c l k # a n d cke. f o r maximum pow e r sav i ng, the us e r has t h e o p tion of d isa b ling the dll p r i o r to enter i ng pow e r - dow n . in th a t case the dll must be en a bl e d and reset aft e r exiting p o wer - d o wn, and 1000 cyc l e s must o cc u r before a read c o mma n d c a n be issu e d . in p o wer - down mo d e , cke l o w and a sta b le cl o c k si g nal m u st be m a intai n ed a t the i nputs of t h e g d dr3 graph i cs ram, all the other i n put s i gna l s a r e Dd o n t c a re. po w e r d o wn duration i s l i mit e d by the refresh re q u ireme n ts of the d e vice. the power - d o wn state is synchr o nous l y e xited w h en cke i s r e gistered high (along with a nop or desel com m and). a v a li d ex e c ut a bl e comma n d m a y b e a ppl i e d t xpn l a t e r. 6. 22 .1 power down command www.datasheet.co.kr datasheet pdf - http://www..net/
W641GG2JB 1 - gbit gddr 3 graphics sdram publication release date: apr, 22 , 20 11 - 92 - revision a01 - 002 6. 22 .2 power - down mode www.datasheet.co.kr datasheet pdf - http://www..net/
W641GG2JB 1 - gbit gddr 3 graphics sdram publication release date: apr, 22 , 20 11 - 93 - revision a01 - 002 7 electrical characteristics 7 .1 a bsolute maximum ratings and operation conditions 7.1.1 absolute maxi m um rating p a ram e ter symbol rating unit min. m a x. p o wer supp l y vo l t a g e v dd - 0.5 2.5 v p o wer supp l y vo l t a ge for output buffer v d dq - 0.5 2.5 v in p u t vo l t a g e v in - 0.5 2.5 v ou tput voltage v out - 0.5 2.5 v stor a ge t e m p erature t stg - 55 + 150 c j u nction t e mperature t j +1 2 5 c case temperature tcase 0 +105 c s h ort cir c uit output current i out 5 0 ma att e ntio n : st r ess e s abo v e the max. valu e s listed h e r e m ay cause p e rm a n e nt da m a ge to the de v i c e . expo s u r e to a b s o lute m a xi m u m r a ting conditions for e x tended p e rio d s m a y a ffect de v i ce rel i a b il i ty. m a xim u m rat i n g s a re ab s o lute ratings; e xce e ding o n ly o n e of the s e v a l u es may cause ir r ev e rsible d a m a ge to the int e gr a ted c i r c u i t. 7 .2 dc operation conditions 7 .2.1 recommended power & dc operation conditions 7.2.1.1 power & dc operation cond i tions (0 c t c 1 05 c) p a rameter sym b ol l imit values un i t n o te m i n. ty p. m a x. p o wer supp l y vo l t a g e v dd / v d d q 1.7 1 .8 1 . 9 v 1 , 2, 3 r e f e r en ce v o l t a g e v ref 0.69 * v ddq 0 .7 1 * v d dq v 4 ou t p ut lo w v o l t a g e v ol(dc) 0 . 8 v 3 in p u t l eaka g e c u rrent i il C + 5 .0 ? 5 clk in p u t l eaka g e c u rrent i i l c C + 5 .0 ? outp u t le a kage curre n t i ol C + 5 .0 ? 5 notes : 1. under all conditions v ddq must be less than o r equal to v dd . 2. v d dq tracks with v d d . ac par a meters are m e asu r ed with v dd a nd v d dq tied together . 3. for 1.8 v v d d / v d d q po w er supply . 4 . v r ef is expect e d to equal 7 0 % of v d d q for the transmitting device a nd to track variations in the dc level of the same. pe a k - to - peak noise on v r ef may n ot exceed 2% v ref ( dc ) . t hus, f r om 7 0 % of v d d q , v ref is allowed 1 9mv for d c e rror a n d an additional 27mv for ac noise . 5 . i il and i o l a r e measured w i th odt disabled . www.datasheet.co.kr datasheet pdf - http://www..net/
W641GG2JB 1 - gbit gddr 3 graphics sdram publication release date: apr, 22 , 20 11 - 94 - revision a01 - 002 7 .3 dc & ac logic input levels 7.3.1 dc & ac logic input levels (0 c t c 1 05 c) p a ram e ter s ym b o l l im it v a l u es u n it n ote min. max. in p u t l ogic h i gh voltag e , dc v ih ( d c) v ref + 0.15 v 1, 2 in p u t l ogic l o w vo l t a ge, dc v il ( d c) v ref - 0 . 1 5 v 1, 2 in p u t l ogic h i gh voltag e , ac v ih ( a c) v ref + 0.25 v 1, 3 , 4 in p u t l ogic l o w vo l t a ge, ac v il ( a c ) v ref - 0.25 v 1, 3 , 4 input logic high, dc, reset pin v ihr ( dc) 0 . 6 5 v ddq v d d q + 0 . 3 v in p u t l ogic l o w, dc, reset pin v ilr (dc) - 0 .3 0 . 35 v d d q v in p u t l ogic hi g h, d c , mf pin v ih m f (dc) v dd v dd + 0 .3 v 5 in p u t l ogic l o w, d c, mf pin v ilmf (dc) C 0 .3 0 v notes : 1. for 1.8 v v d d / v d d q po w er supply . 2 . the d c values define wh e re the input slew rate requireme n ts a r e im p osed, and the input sig n al must not violate these levels in or der to mai n tain a val i d le v e l . 3 . input slew rate = 3 v / n s. if t he input slew rate is l e ss th a n 3 v/ns, inp u t timing may b e compr o mised. a ll slew r ates a r e measu r ed be t ween v i l (ac) and v i h (a c) . 4 . v i h overshoot: v i h (ma x ) = v dd q +0.5v for a pulse width 5 00ps a nd the pulse wi d th ca n not be g r eater th a n 1/3 of the cycle r a te. v il unde r shoo t : v il (min) = 0 v for a pulse width 500ps and the pulse width cannot be greater than 1/3 of the cycle rate. 5 . the mf pin must be hard - wired on board to either v dd or v s s . www.datasheet.co.kr datasheet pdf - http://www..net/
W641GG2JB 1 - gbit gddr 3 graphics sdram publication release date: apr, 22 , 20 11 - 95 - revision a01 - 002 7 .4 differential clock dc and ac levels 7.4.1 differential clock dc and ac input conditions (0 c t c 105c) p a ram e ter s ym b o l l imit v a l u es u n it n o te min. max. clock i n put m i d - point voltag e , clk a n d c l k # v mp ( d c) 0. 7 v d d q C 0.10 0 . 7 v ddq + 0. 10 v 1 clock i n put v o ltage l e vel, c l k a nd clk # v in ( d c) 0.42 v d d q + 0. 3 v 1 , 2 clock dc i n put d iffer e n tial volta g e, c l k a n d clk # v id ( d c) 0 .3 v d d q v 1 clock ac in p u t d i ffere n t i al voltag e , clk a n d c l k # v id ( a c) 0 .5 v d d q + 0 . 5 v 1 , 2, 3 ac d i ffere n t i al crossing p o int in p u t vo l t a g e v ix (ac) 0.7 v d d q C 0.15 0 . 7 v ddq + 0. 15 v 1 , 2, 4 notes : 1. all voltag e s r eferenced to v s s . 2. for 1.8 v v d d / v d d q po w er supply . 3 . v id is the m a gnitu d e of the differ e nce b e tween the input level o n clk and the input level on cl k # . 4 . the value of v ix is expected to equal 0.7 v d dq o f the tra n smitti n g device and must tr a c k v a riations in the dc level of the same. 7 .5 output test conditions 6 0 o h m v d d q t e s t p o i n t d q d q s www.datasheet.co.kr datasheet pdf - http://www..net/
W641GG2JB 1 - gbit gddr 3 graphics sdram publication release date: apr, 22 , 20 11 - 96 - revision a01 - 002 7 .6 p in capacitances 7.6.1 pin c apac i tances (vd d q = 1.8 v, ta = 25c, f = 1 m hz) p a ram e ter symb o l min. max. unit note in p u t c a pacitanc e : a 0 - a11,a12, , ba0 - 2, c k e, c s # , ca s # , ras # , w e # , cke, res,clk,clk # ci,c c k 1.0 2 .5 pf in p u t c a pacitanc e : dq 0 - d q 3 1 , rdqs0 - rdqs3, wdqs 0 - wdqs 3 , dm0 - dm3 cio 2 .0 3.0 p f 7 .7 driver current characteristics 7 .7.1 driver iv characteristics at 40 ohms f i g u r e repres e n ts the driver p u ll - d o wn a n d pu l l - up iv char ac ter i stics u nder p rocess, voltage and t e mperature b e st and worst c a se con d it i ons. t h e actual driver pul l - d own a nd pu l l - up curre n t must lie betwe e n these two b ou n ding curves. t h e v a lue of the extern a l zq resistor is 240 , s e tting the n o minal d river o u tput imped a nce to 4 0 . 7.7.1.1 40 ohm driver pull - down and pull - up characteristics p u l l - d o w n c h a r a c t e r s t i c s 0 5 1 0 1 5 2 0 2 5 3 0 3 5 4 0 4 5 5 0 0 . 0 0 . 5 1 . 0 1 . 5 2 . 0 v o u t ( v ) i o u t ( m a ) p u l l - u p c h a r a c t e r s t i c s - 5 0 - 4 5 - 4 0 - 3 5 - 3 0 - 2 5 - 2 0 - 1 5 - 1 0 - 5 0 0 . 0 0 . 5 1 . 0 1 . 5 2 . 0 v d d q - v o u t ( v ) i o u t ( m a ) www.datasheet.co.kr datasheet pdf - http://www..net/
W641GG2JB 1 - gbit gddr 3 graphics sdram publication release date: apr, 22 , 20 11 - 97 - revision a01 - 002 ta ble l i s ts t h e n u m e ric a l v a l u es o f t h e m i nimum a n d maximum a l low e d val u es of the o u t p ut driver pu l l - down and p u ll - up iv characteristics. 7.7.1.2 prog r ammed driver iv characteristics at 40 ohm v olta g e (v) p u ll - d o wn curre n t ( m a) p u ll - up current (ma) minimum maximum minimum ma x i m u m 0.1 2 .32 3 .04 - 2.44 - 3 . 2 7 0.2 4 .56 5 .98 - 4.79 - 6 . 4 2 0.3 6 .69 8 .82 - 7.03 - 9 . 4 5 0.4 8 .74 11.56 - 9.18 - 1 2 .37 0.5 1 0 . 7 0 14.19 - 11.23 - 1 5.17 0.6 1 2 . 5 6 16.72 - 13.17 - 1 7.83 0.7 1 4 . 3 4 19.14 - 15.01 - 2 0.37 0.8 1 6 . 0 1 21.44 - 16.74 - 2 2.78 0.9 1 7 . 6 1 23.61 - 18.37 - 2 5.04 1.0 1 9 . 1 1 26.10 - 19.90 - 2 7.17 1.1 2 0 . 5 3 28.45 . 2 1.34 - 2 9.17 1.2 2 1 . 9 2 30.45 - 22.72 - 3 1.25 1.3 2 3 . 2 9 32.73 - 24.07 - 3 3.00 1.4 2 4 . 6 5 34.95 - 25.40 - 3 5.00 1.5 2 6 . 0 0 37.10 - 26.73 - 3 7.00 1.6 2 7 . 3 5 39.15 - 28.06 - 3 9.14 1.7 2 8 . 7 0 41.01 - 29.37 - 4 1.25 1.8 3 0 . 0 8 42.53 - 30.66 - 4 3.29 1.9 43.71 - 4 5 .23 2.0 44.89 - 4 7 .07 7.8 termination current characteristics 7 . 8 . 1 t ermination iv characteristic at 60 ohms f i g u r e r e presents t h e dq termin a t i on pu l l - up iv ch a ract e rist i c u nd e r p r o cess, vo l t a ge and t e m p erature b e st and worst case c o nd i ti o n s. the actual d q t e rm i nation p u ll - up curre n t must l i e betwe e n th e se two b ou n ding c u rv e s . t h e v a lue o f the external zq r e sist o r i s 240 , sett i ng the n o minal dq termin a ti o n imp e dance to 6 0 . (exten d ed mode reg i ster p r o g rammed to z q /4). www.datasheet.co.kr datasheet pdf - http://www..net/
W641GG2JB 1 - gbit gddr 3 graphics sdram publication release date: apr, 22 , 20 11 - 98 - revision a01 - 002 7. 8 . 1 .1 60 ohm active termination characteristic table lists the numerical values of the minimum and maximum allowed values of the output driver termination iv characteristic. 7. 8 . 1 .2 prog r ammed terminator characteristics at 60 ohm v oltage (v) terminator pull - u p curr e nt (ma) volta g e (v) te r minator pull - up current (ma) minim u m maximum minim u m maximum 0.1 - 1.63 - 2.18 1 .1 - 1 4.23 - 1 9 . 4 5 0.2 - 3.19 - 4.28 1 .2 - 1 5.14 - 2 0 . 8 3 0.3 - 4.69 - 6.30 1 .3 - 1 6.04 - 2 2 . 0 0 0.4 - 6.12 - 8.25 1 .4 - 1 6.94 - 2 3 . 3 3 0.5 - 7.49 - 10.11 1.5 - 1 7 .82 - 2 4 . 6 7 0.6 - 8.78 - 11.89 1.6 - 1 8 .70 - 2 6 . 0 9 0.7 - 1 0 . 0 1 - 13.58 1.7 - 1 9 .58 - 2 7 . 5 0 0.8 - 1 1 . 1 6 - 15.19 1.8 - 2 0 .44 - 2 8 . 8 6 0.9 - 1 2 . 2 5 - 16.69 1.9 - 3 0 . 1 5 1.0 - 1 3 . 2 7 - 18.11 2.0 - 3 1 . 3 8 6 0 o h m t e r m i n a t i o n c h a r a c t e r i s t i c - 3 5 - 3 0 - 2 5 - 2 0 - 1 5 - 1 0 - 5 0 0 . 0 0 . 5 1 . 0 1 . 5 2 . 0 v d d q - v o u t ( v ) i o u t ( m a ) www.datasheet.co.kr datasheet pdf - http://www..net/
W641GG2JB 1 - gbit gddr 3 graphics sdram publication release date: apr, 22 , 20 11 - 99 - revision a01 - 002 7 .8 .2 t ermination iv characteristic at 120 ohms f i g u r e represe n ts the dq o r add/ c m d t e rmi n ation pull - up iv ch a ract e rist i c un d er process, volta g e a n d temperature b e st and w o rst case cond i t i ons. the actual termi n a t i on pu l l - up curr e nt m u st l i e betw e en these two bou n di n g curves. the value of the extern a l zq r e s i stor is 2 4 0 , sett i ng the n o m i nal t e rmi n ation impe d ance to 120 . (exte n ded mode reg i ster programmed t o z q /2 f o r dq te rminations or cke = 0 at the r es tra n sit i on dur i ng power - up for add/cmd termi n a t i ons). 7.8. 2.1 120 ohm active termination characteristic 1 2 0 o h m t e r m i n a t i o n c h a r a c t e r i s t i c - 1 6 - 1 4 - 1 2 - 1 0 - 8 - 6 - 4 - 2 0 0 . 0 0 . 5 1 . 0 1 . 5 2 . 0 v d d q - v o u t ( v ) i o u t ( m a ) www.datasheet.co.kr datasheet pdf - http://www..net/
W641GG2JB 1 - gbit gddr 3 graphics sdram publication release date: apr, 22 , 20 11 - 100 - revision a01 - 002 ta ble lists the n u m e rical val u es of the min i m u m a n d m a ximum a llo w ed valu e s o f the t e rm i nation iv c h aracteristic. 7.8.2 .2 programmed te r minator characteristics of 120 ohm v oltage (v) terminator pull - u p curr e nt (ma) volta g e (v) te r minator pull - up current (ma) minim u m maximum minim u m maximum 0.1 - 0.81 - 1.09 1 .1 - 7 . 1 1 - 9.72 0.2 - 1.60 - 2.14 1 .2 - 7 . 5 7 - 1 0 . 4 2 0.3 - 2.34 - 3.15 1 .3 - 8 . 0 2 - 1 1 . 0 0 0.4 - 3.06 - 4.12 1 .4 - 8 . 4 7 - 1 1 . 6 7 0.5 - 3.74 - 5.06 1 .5 - 8 . 9 1 - 1 2 . 3 3 0.6 - 4.39 - 5.94 1 .6 - 9 . 3 5 - 1 3 . 0 5 0.7 - 5.00 - 6.79 1 .7 - 9 . 7 9 - 1 3 . 7 5 0.8 - 5.58 - 7.59 1 .8 - 1 0.22 - 1 4 . 4 3 0.9 - 6.12 - 8.35 1 .9 - 1 5 . 0 8 1.0 - 6.63 - 9.06 2 .0 - 1 5 . 6 9 7 . 8.3 t ermination iv characteristic at 240 ohms f i g u r e re p resents the ad d / cmd terminati o n p u ll - up iv c h aracter i st i c u nder proc e ss, voltage a nd t e m p erature b e st and worst case con d itions. the a ctu a l add/ c m d termin a ti o n pull - up curr e nt must l ie betwe e n th e se two b oun d ing curves. t h e v a lue o f the external zq res i stor is 240 , sett i ng t h e nomi n al terminati o n imped a nce to 240 . ( c k e = 1at the res t r ansition duri n g p o wer - up for ad d / cmd terminati o ns). 7. 8 . 3.1 240 ohm active termination characteristic 2 4 0 o h m t e r m i n a t i o n c h a r a c t e r i s t i c - 8 . 0 - 7 . 0 - 6 . 0 - 5 . 0 - 4 . 0 - 3 . 0 - 2 . 0 - 1 . 0 0 0 . 0 0 . 5 1 . 0 1 . 5 2 . 0 v d d q - v o u t ( v ) i o u t ( m a ) www.datasheet.co.kr datasheet pdf - http://www..net/
W641GG2JB 1 - gbit gddr 3 graphics sdram publication release date: apr, 22 , 20 11 - 101 - revision a01 - 002 ta ble l i sts the n u merical val u es of t h e min i m u m and m a ximum al l o wed valu e s of t h e add/cmd terminati o n iv c h aracteristic. 7. 8 . 3.2 pr og ra m med te rmi n a to r c h ar a c te r i s t i c s at 2 40 oh m v oltage (v) t erminator pull - u p current (ma) v oltage (v) t erminator pull - up current (ma) mi n i mum maximum m i n imum maximum 0.1 - 0. 4 1 - 0.55 1 .1 - 3. 5 6 - 4.86 0.2 - 0. 8 0 - 1.07 1 .2 - 3. 7 9 - 5.21 0.3 - 1. 1 7 - 1.58 1 .3 - 4. 0 1 - 5.50 0.4 - 1. 5 3 - 2.06 1 .4 - 4. 2 3 - 5.83 0.5 - 1. 8 7 - 2.53 1 .5 - 4. 4 6 - 6.17 0.6 - 2. 2 0 - 2.97 1 .6 - 4. 6 8 - 6.52 0.7 - 2. 5 0 - 3.40 1 .7 - 4. 9 0 - 6.88 0.8 - 2. 7 9 - 3.80 1 .8 - 5. 1 1 - 7.21 0.9 - 3. 0 6 - 4.17 1 .9 - 7.54 1.0 - 3. 3 2 - 4.53 2 .0 - 7.85 www.datasheet.co.kr datasheet pdf - http://www..net/
W641GG2JB 1 - gbit gddr 3 graphics sdram publication release date: apr, 22 , 20 11 - 102 - revision a01 - 002 7. 9 operating current ratings sym. parameter /condition typ . unit notes 650 700 800 i dd0 one bank activate precharge current: tck = tck(min); trc = trc(min); cke = high; data bus inputs are switching; address and command inputs are switching; /cs is high between valid commands 320 335 360 ma i dd1 one bank activate read precharge current: tck= tck(min); trc = trc(min); cke = high; 1 bank activated; single read burst with data bus switching, address and command inputs are switching; /cs is high between valid commands; iout = 0ma 330 345 380 ma 2 i dd2p precharge power - down current: tck = tck(min); all banks idle; cke = low; all other inputs are high 140 150 160 ma i dd 2 n precharge standby current in non power - down mode. 190 200 220 ma i dd3n active standby current: tck = tck(min); 1 bank active; cke = high; all other inputs are high 285 300 330 ma i dd4r burst read current: tck = tck(min); cke = high; continuous read burst across banks with data bus switching; address and command inputs are switching; iout = 0 ma 495 520 550 ma 2 i dd4w write burst current: tck = tck(min); cke = high; continuous write burst across banks with data bus switching; address and command inputs are switching 495 520 550 ma i dd 5d auto refresh current at trefi. 380 400 435 ma i dd6 self refresh current: cke = low; all other inputs are high 40 40 40 ma notes: 1. idd specifications are tested after the device is properly initialized. 2. measured with open outputs and odt off. 3. low is defined as inputs stable at vil(max) . high is defined as inputs stable at vih(min) . switching is defined as inputs changing between high and low every cloc k cycle for address and command inputs, and inputs changing with 50% of each data transfer for dq. www.datasheet.co.kr datasheet pdf - http://www..net/
W641GG2JB 1 - gbit gddr 3 graphics sdram publication release date: apr, 22 , 20 11 - 103 - revision a01 - 002 7 .1 0 ac timings p a ram e ter cas lat e ncy symbol limit valu e s unit note 650 7 0 0 8 0 0 m h z min max min max min max clock and clo c k enable system fre q ue n cy cl =11 f ck 1 1 4 5 0 700 m h z 1 cl =10 f ck 1 0 4 5 0 700 450 800 m h z 1 cl = 9 f ck9 450 650 m h z 1 clock c y cle to cycle pe r i od jitter t ji t (c c ) 0.06 0.06 0.06 t ck 2 , 3 clock hi g h l e vel wi d th t ch 0.45 0 .45 0 .45 t ck 2 , 3,4 clock low l e v e l width t cl 0.45 0 .45 0 .45 t ck 2 , 3,4 m i nimum clock half peri o d t hp 0.45 0 .45 0 .45 t ck 3 c o mm an d an d a d dr e s s s e t u p a n d hold t imi n g a d dress/comman d i n pu t s e t u p t i me t is 0.35 0 .35 0 .35 ns 5 , 6 a d dress/command i n put hold time t ih 0.35 0 .35 0 .35 ns 5 , 6 a d dress/command i n put pulse w i dth t ipw 0.7 0.7 0.7 t ck 4 m o d e r e g i ste r se t t im ing m o de register set c y cle time t m r d 6 6 6 t ck 7 , 8 m o de register set to read timing t m r dr 12 1 2 1 2 t ck 7 r o w tim i ng ro w cycl e t i me t rc 37 3 7 37 t ck row act i ve time t ras 27 2 7 27 t ck 9 a c t(a) to act(b) command p e riod t r r d 7 7 8 t ck a c t(a) to act(b) c o mma n d p e riod ( d iff e r e nt rank ) t r r d _ rr 1 1 1 t ck 1 2 row prechar g e time t rp 12 1 2 14 t ck row to c o lumn de l a y time for rea d s t r c d r d 11 1 1 13 t ck row to c o lumn de l a y time for writes t r c dwr 9 9 9 t ck fo u r active wi n dows with i n r ank t faw 35 3 5 35 t ck co l u m n t i m i ng cas( a ) to cas(b) c o mm a nd p e r i od t c c d bl/2 bl/2 bl/2 t ck 1 0 inter n al write to r e ad command d e lay t wtr 6 6 6 t ck 1 1 write to r e ad command d e lay (different rank) t wt r_ rr 1 1 1 t ck 1 0 write to write c o mm a nd de l a y ( d iffer e nt ra n k ) t wt w _ rr 2 2 2 t ck 1 0 read to write command d e lay t rtw t r t w(m i n) = cl + bl/2+ 2 - wl t ck 1 4 read to re a d c o mm a nd de l a y ( d iffer e nt ra n k) t rt r _rr 2 2 2 t ck 1 0 write cycle t i ming para m e ters for data and data strobe w rite com m and to first wdqs la t ching t r ansition t dqss w l C 0.25 wl+ 0 .25 w l C 0.25 wl+ 0 .25 w l C 0.25 wl+ 0 .25 t ck www.datasheet.co.kr datasheet pdf - http://www..net/
W641GG2JB 1 - gbit gddr 3 graphics sdram publication release date: apr, 22 , 20 11 - 104 - revision a01 - 002 p a ram e ter cas lat e ncy symbol limit valu e s unit note 650 7 0 0 8 0 0 m h z min max min max min max data - in a n d d a ta m a sk to w dqs setup time t ds 0.18 0 .18 0 .18 ns 5 , 13 data - in and data m a s k to w dqs hold t i m e t dh 0.18 0 .18 0 .18 ns 5 , 13 data - in a n d d m i n put p u lse w i dth ( e ach in p u t) t dipw 0.40 0 .40 0 .40 t ck dqs in p u t l o w pulse w i dth t dqsl 0.40 0 .40 0 .40 t ck dqs in p u t h i gh p u lse width t dqsh 0.40 0 .40 0 .40 t ck dqs write preamb l e time t wpre 0.75 1.25 0.75 1.25 0.75 1.25 t ck dqs write postamble time t wpst 0.75 1.25 0.75 1.25 0.75 1.25 t ck write recovery t i me t wr 10 1 0 1 0 t ck 1 1 read c ycle timing p a ram e ters for d a ta and data strobe data a cce s s time from clock t ac C 0.25 0.25 C 0 . 2 5 0 .25 C 0 . 2 5 0 .25 n s rea d pre a m b le t rp r e 0.75 1.25 0.75 1.25 0.75 1.25 t ck 4 read postamb l e t rpst 0.75 1.25 0.75 1.25 0.75 1.25 t ck data - out high i m p ed a nce t i me from clk t hz t a c min t a c max t acm i n t a c max t acm i n t a c max ns data - out low imp e dance time fr o m c l k t lz t a c min t a c max t acm i n t a c max t acm i n t a c max ns dqs ed g e to c l ock e dge skew t dqsck C 0.25 0.25 C 0 . 2 5 0 .25 C 0 . 2 5 0 .25 n s dq s ed g e t o o u t p u t d at a e dg e skew t dqsq 0 .16 0 .16 0 .16 ns 1 5 data hold skew factor t qhs 0 .16 0 .16 0 .16 ns data output hold time from dqs t qh t h p C t qhs ns refre s h/power down timing refresh period (8192 cycles) t ref 3 2 3 2 3 2 m s av e rage p e r i od i c auto refresh i n terv a l t refi 3.9 3 .9 3 .9 s delay from aref to next act/ aref t rfc 59 5 9 5 9 ns s e lf r e fr e s h exit t i me t xsc 10 0 0 1 0 00 1 0 00 t ck p o wer down exit time t xpn 6 6 6 t ck other timing p a ram e t e rs res to cke setup timing t ats 10 1 0 1 0 ns res to cke hold timing t ath 10 1 0 1 0 ns termi n a tion u p date keep out timing t ko 10 1 0 1 0 ns rev. id e m rs to dq on timing t rid o n 2 0 20 20 ns rev . i d emr s t o d q o ff t i m i ng t r i d o ff 2 0 20 20 ns www.datasheet.co.kr datasheet pdf - http://www..net/
W641GG2JB 1 - gbit gddr 3 graphics sdram publication release date: apr, 22 , 20 11 - 105 - revision a01 - 002 1. f c k (m i n ) , f c k ( max) for dll on mode . 2 . clk and c lk # inp u t slew r ate must be gr e ater than 3 v/ns . 3 . t hp is the lesser o f t c l minim u m and t ch minimum actually applied to the device clk,clk# inputs. 4 . timing is calculated for a clock f r equecy of 700 mhz . 5 . the input r efer e nce level f o r signals other than clk and clk# is v ref. 6 . command/ad d ress input slew rate = 3 v / n s. if t h e slew r ate is less than 3 v/ns, timing is no longer ref e renced to the midpoint but to the v i l(a c ) max i mum and v i h (a c ) m i n i mum p o i nts . 7 . this value of t m rd a p plies only to the case whe r e the " dll reset " bit is not activated . 8 . t mrd is defined f r om mrs to any other c o mmand then read . 9 . t ra s ,m a x is 8 * t r e fi . 1 0 . t ccd is either f o r gapless consecu t ive rea d s or gap l ess consecutive writes . 1 1 . wtr and t w r start at the first rising edge of clk after the last valid (falling) wdqs edge o f the slow e s t wdqs signal . 1 2 . this parameter is defined for commands i s s u ed to ra n k m following rank n wh e re m n. for a l l other type o f access, stand a rd timing param e ters do apply . 1 3 . dq and dm input slew rat e s must not deviate fr o m w d qs by m o re than 10 pe r c e nt. if the dq/dm/wdqs slew rate is less than 3 v/ n s, timing is no lo n ger r eferenced to t h e midp o int b u t to the v il( a c) maxim u m and v ih( a c) min i m u m po i n ts . 1 4 . please r ound up t r t w to t he next int e ger of t ck . 1 5 . this parameter is defined p e r byte . 16. tac +/ - 290ps when vddmax. 17. input slew rate = 2.2v/ns. if tis/tih higher than 550ps. www.datasheet.co.kr datasheet pdf - http://www..net/
W641GG2JB 1 - gbit gddr 3 graphics sdram publication release date: apr, 22 , 20 11 - 106 - revision a01 - 002 8 . package spec ification package outline tf bga 136 (10x14 mm 2 , ball pitch:0.8mm, ? =0.45mm ) 2 . 2 m a x l e a d f r e e s o l d e r b a l l s ( g r e e n s o l d e r b a l l s ) 1 ) b a d u n i t m a r k i n g ( b u m ) ( l i g h t = g o o d ) 2 ) m i d d l e o f p a c k a g e s e d g e s 3 ) p a c k a g e o r i e n t a t i o n m a r k a 1 4 ) s b a - f i d u c i a l ( s o l d e r b a l l a t t a c h ) 5 ) b a r e c o r e a r e a 6 ) s o l d e r b a l l d i a m e t e r r e f e r s t o p o s t r e f l o w c o n d u c t i o n a b c 0 . 1 c 0 . 2 0 . 1 c o 0 . 1 5 m o 0 . 0 8 m c a c b s e a t i n g p l a n e 1 . 2 m a x . 0 . 3 1 m i n . o 0 . 4 5 0 . 0 5 6 ) 2 ) 4 ) 5 ) 3 ) 1 ) 2 ) 1 6 x 0 . 8 = 1 2 . 8 1 4 0 . 8 0 . 8 1 0 1 1 x 0 . 8 = 8 . 8 9 . 2 0 . 1 2 m a x . 0 . 1 8 m a x . www.datasheet.co.kr datasheet pdf - http://www..net/
W641GG2JB 1 - gbit gddr 3 graphics sdram publication release date: apr, 22 , 20 11 - 107 - revision a01 - 002 9 . ordering information p art number d escription W641GG2JB - 14 1gb gddr3 sdram note: for pad information of kgd, please contact sales representative . www.datasheet.co.kr datasheet pdf - http://www..net/
W641GG2JB 1 - gbit gddr 3 graphics sdram publication release date: apr, 22 , 20 11 - 108 - revision a01 - 002 10 . revision history version date page description a 01 - 001 0 3 / 28 /201 1 all product datasheet for customer . a01 - 002 04/22/2011 32 93 102 103,104 add tsac value. add tcase . add 800 mhz in dc table. add 800 mhz in ac table. www.datasheet.co.kr datasheet pdf - http://www..net/
W641GG2JB 1 - gbit gddr 3 graphics sdram publication release date: apr, 22 , 20 11 - 109 - revision a01 - 002 important notice winbond products are not designed, intended, authorized or warranted for use as components in systems or equipment intended for surgical implantation, atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, or for other applications intended to support or sustain life. further more, winbond products are not intended for applications wherein failure of winbond products could result or lead to a situation whe rein personal injury, death or severe property or environmental damage could occur. winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify winbond for any damages resulting from such improper use or sales. ----------------------------------------------------------------------------------------------------------------------------- -------------------- please note that all data and specifications are subject to change without notice. all the trademarks of products and companies mentioned in the datasheet belong to their respective owners. www.datasheet.co.kr datasheet pdf - http://www..net/

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